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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: CyWs15jouB9Yof8ccjXzAOOVmW7tDlrYVSIfvqoZH34whcJXxgH0PjIuwVo8Wwk80Crece8KUaxv3SMxqOz97ALtRvzxKuy3YRriV+lcDpRCxl6jrIz5/8aQN6JgyY3AfNy4cMz22qrqcwm2TATlLqY+yspVHJXoolTjMhVQYd7C0EORycGhBp5Pwld3xnMXBZ8wSEncUrN4YxU3XdxH6QU5uTBKd3zdQbtDA17iUFma2+PqrvPdxm7QgryupOnL34mRd+Qn46xQ4GVblZn27x+ZTFpEUfLb+G68sgp44V+ye+2l3kBzrbn6TRwIx8uRrQBMlYTPah8TnvvSg/lPn+nCTSEcKKxw35fo/7gTbVZnyHqRiy8kZQpzuwW7/IKJMxgXI8Y1L3zn5A3gOERo8mWrNhGEfviAkw0czA1U0dtm1lrf3XbWicpUVx3fN3Sj Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5c3950ac-a054-477d-8721-08d75c09e24a X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Oct 2019 00:49:41.5531 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 7q+DHWhhtqMGdplegKLq36bnUjvIFoNbj6l7SC/QobHjX2HRMN0fqYCjfhcZnNIxmiCmbE/z2LnmfpmbzLljlA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4182 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Shawn Guo > Sent: Monday, October 28, 2019 6:51 PM > To: Fancy Fang > Cc: sboyd@kernel.org; linux-clk@vger.kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > mturquette@baylibre.com; s.hauer@pengutronix.de; kernel@pengutronix.de; > dl-linux-imx > Subject: Re: [PATCH v4] clk: imx7ulp: do not export out IMX7ULP_CLK_MIPI_= PLL > clock >=20 > On Mon, Oct 28, 2019 at 08:07:59AM +0000, Fancy Fang wrote: > > The mipi pll clock comes from the MIPI PHY PLL output, so > > it should not be a fixed clock. > > > > MIPI PHY PLL is in the MIPI DSI space, and it is used as > > the bit clock for transferring the pixel data out and its > > output clock is configured according to the display mode. > > > > So it should be used only for MIPI DSI and not be exported > > out for other usages. > > > > Signed-off-by: Fancy Fang > > --- > > ChangeLog v3->v4: > > * Add some comments to 'IMX7ULP_CLK_MIPI_PLL' > > clock. > > > > Documentation/devicetree/bindings/clock/imx7ulp-clock.txt | 1 - > > drivers/clk/imx/clk-imx7ulp.c | 3 +-- > > include/dt-bindings/clock/imx7ulp-clock.h | 6 ++++++ > > 3 files changed, 7 insertions(+), 3 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > index a4f8cd478f92..93d89adb7afe 100644 > > --- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt > > @@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 { > > <&scg1 IMX7ULP_CLK_APLL_PFD0>, > > <&scg1 IMX7ULP_CLK_UPLL>, > > <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, > > - <&scg1 IMX7ULP_CLK_MIPI_PLL>, > > <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, > > <&scg1 IMX7ULP_CLK_ROSC>, > > <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; > > diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ul= p.c > > index 2022d9bead91..459b120b71d5 100644 > > --- a/drivers/clk/imx/clk-imx7ulp.c > > +++ b/drivers/clk/imx/clk-imx7ulp.c > > @@ -28,7 +28,7 @@ static const char * const scs_sels[] =3D { "dummy", > "sosc", "sirc", "firc", "dumm > > static const char * const ddr_sels[] =3D { "apll_pfd_sel", "upll", }; > > static const char * const nic_sels[] =3D { "firc", "ddr_clk", }; > > static const char * const periph_plat_sels[] =3D { "dummy", "nic1_bus_= clk", > "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", }; > > -static const char * const periph_bus_sels[] =3D { "dummy", "sosc_bus_c= lk", > "mpll", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk= ", }; > > +static const char * const periph_bus_sels[] =3D { "dummy", "sosc_bus_c= lk", > "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_cl= k", }; > > static const char * const arm_sels[] =3D { "divcore", "dummy", "dummy= ", > "hsrun_divcore", }; > > > > /* used by sosc/sirc/firc/ddr/spll/apll dividers */ > > @@ -75,7 +75,6 @@ static void __init imx7ulp_clk_scg1_init(struct > device_node *np) > > clks[IMX7ULP_CLK_SOSC] =3D imx_obtain_fixed_clk_hw(np, "sosc"); > > clks[IMX7ULP_CLK_SIRC] =3D imx_obtain_fixed_clk_hw(np, "sirc"); > > clks[IMX7ULP_CLK_FIRC] =3D imx_obtain_fixed_clk_hw(np, "firc"); > > - clks[IMX7ULP_CLK_MIPI_PLL] =3D imx_obtain_fixed_clk_hw(np, "mpll"); > > clks[IMX7ULP_CLK_UPLL] =3D imx_obtain_fixed_clk_hw(np, "upll"); > > > > /* SCG1 */ > > diff --git a/include/dt-bindings/clock/imx7ulp-clock.h > b/include/dt-bindings/clock/imx7ulp-clock.h > > index 6f66f9005c81..e9ef62f211fe 100644 > > --- a/include/dt-bindings/clock/imx7ulp-clock.h > > +++ b/include/dt-bindings/clock/imx7ulp-clock.h > > @@ -49,7 +49,13 @@ > > #define IMX7ULP_CLK_NIC1_DIV 36 > > #define IMX7ULP_CLK_NIC1_BUS_DIV 37 > > #define IMX7ULP_CLK_NIC1_EXT_DIV 38 > > + > > +/* mpll clock is a special clock comes from > > + * mipi DPHY PLL and should be used only for > > + * mipi dsi instead of any other peripheral. > > + */ > > #define IMX7ULP_CLK_MIPI_PLL 39 > > + >=20 > The point of comment is to tell that the clock ID is unsupported and > shouldn't be used in DT. >=20 > I reworded the comment and applied the patch. OK. Thank you. Best regards, Fancy Fang >=20 > Shawn >=20 > > #define IMX7ULP_CLK_SIRC 40 > > #define IMX7ULP_CLK_SOSC_BUS_CLK 41 > > #define IMX7ULP_CLK_FIRC_BUS_CLK 42 > > -- > > 2.17.1 > >