From: Aisheng Dong <aisheng.dong@nxp.com>
To: Peng Fan <peng.fan@nxp.com>,
"shawnguo@kernel.org" <shawnguo@kernel.org>,
"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
"festevam@gmail.com" <festevam@gmail.com>,
Abel Vesa <abel.vesa@nxp.com>,
"robh+dt@kernel.org" <robh+dt@kernel.org>
Cc: "kernel@pengutronix.de" <kernel@pengutronix.de>,
dl-linux-imx <linux-imx@nxp.com>,
Anson Huang <anson.huang@nxp.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: RE: [PATCH V2 3/4] ARM: imx: imx7ulp: support HSRUN mode
Date: Thu, 17 Sep 2020 04:04:29 +0000 [thread overview]
Message-ID: <AM6PR04MB496611DC4C616CD034A970B9803E0@AM6PR04MB4966.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <1600224517-31465-4-git-send-email-peng.fan@nxp.com>
> From: Peng Fan <peng.fan@nxp.com>
> Sent: Wednesday, September 16, 2020 10:49 AM
>
> Configure PMPROT to let ARM core could run into HSRUN mode.
> In LDO-enabled mode, HSRUN mode is not allowed, so add a check before
> configure PMPROT.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
> arch/arm/mach-imx/pm-imx7ulp.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/mach-imx/pm-imx7ulp.c
> b/arch/arm/mach-imx/pm-imx7ulp.c index 2e756d8191fa..393faf1e8382
> 100644
> --- a/arch/arm/mach-imx/pm-imx7ulp.c
> +++ b/arch/arm/mach-imx/pm-imx7ulp.c
> @@ -11,6 +11,10 @@
>
> #include "common.h"
>
> +#define PMC0_CTRL 0x28
> +#define BM_CTRL_LDOEN BIT(31)
> +
> +#define SMC_PMPROT 0x8
> #define SMC_PMCTRL 0x10
> #define BP_PMCTRL_PSTOPO 16
> #define PSTOPO_PSTOP3 0x3
> @@ -25,7 +29,10 @@
> #define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM)
> #define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM)
>
> +#define BM_PMPROT_AHSRUN BIT(7)
> +
> static void __iomem *smc1_base;
> +static void __iomem *pmc0_base;
>
> int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) { @@ -65,5 +72,13
> @@ void __init imx7ulp_pm_init(void)
> of_node_put(np);
> WARN_ON(!smc1_base);
>
> + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0");
> + pmc0_base = of_iomap(np, 0);
> + WARN_ON(!pmc0_base);
> + of_node_put(np);
> +
> + if (!(readl_relaxed(pmc0_base + PMC0_CTRL) & BM_CTRL_LDOEN))
> + writel_relaxed(BM_PMPROT_AHSRUN, smc1_base + SMC_PMPROT);
When will HSRUN mode be enabled? E.g. RUNM=HSRUN
It seems RUNM will be cleared in the following imx7ulp_set_lpm().
Regards
Aisheng
> +
> imx7ulp_set_lpm(ULP_PM_RUN);
> }
> --
> 2.28.0
next prev parent reply other threads:[~2020-09-17 4:04 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 2:48 [PATCH V2 0/4] imx: support i.MX7ULP HSRUN mode peng.fan
2020-09-16 2:48 ` [PATCH V2 1/4] dt-bindings: fsl: add i.MX7ULP PMC peng.fan
2020-09-17 3:01 ` Aisheng Dong
2020-09-16 2:48 ` [PATCH V2 2/4] ARM: dts: imx7ulp: add pmc node peng.fan
2020-09-17 3:02 ` Aisheng Dong
2020-09-16 2:48 ` [PATCH V2 3/4] ARM: imx: imx7ulp: support HSRUN mode peng.fan
2020-09-17 4:04 ` Aisheng Dong [this message]
2020-09-16 2:48 ` [PATCH V2 4/4] ARM: imx: cpuidle-imx7ulp: Stop mode disallowed when HSRUN peng.fan
2020-09-17 4:11 ` Aisheng Dong
2020-09-22 18:00 ` [PATCH V2 0/4] imx: support i.MX7ULP HSRUN mode Fabio Estevam
-- strict thread matches above, loose matches on Subject: below --
2020-04-13 6:49 [PATCH V2 0/4] ARM: imx7ulp: support " peng.fan
2020-04-13 6:49 ` [PATCH V2 3/4] ARM: imx: " peng.fan
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