From: Sherry Sun <sherry.sun@nxp.com>
To: Michal Simek <michal.simek@xilinx.com>,
"bp@alien8.de" <bp@alien8.de>,
"mchehab@kernel.org" <mchehab@kernel.org>,
"tony.luck@intel.com" <tony.luck@intel.com>,
"james.morse@arm.com" <james.morse@arm.com>,
"rric@kernel.org" <rric@kernel.org>
Cc: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
dl-linux-imx <linux-imx@nxp.com>
Subject: RE: [PATCH 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X Synopsys EDAC DDR
Date: Wed, 20 Apr 2022 06:23:59 +0000 [thread overview]
Message-ID: <AS8PR04MB840489588D0DA46B8FFECFFF92F59@AS8PR04MB8404.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <ab18f598-d4f5-049c-66f3-3ce2d5c01670@xilinx.com>
> > Since zynqmp_get_error_info() is called during CE/UE interrupt, at the
> > end of zynqmp_get_error_info(), it wirtes 0 to ECC_CLR_OFST, which cause
> > the CE/UE interrupts of V3.X Synopsys EDAC DDR been disabled, then the
> > interrupt handler will be called only once, so need to re-enable the
> > interrupts at the end of intr_handler for V3.X Synopsys EDAC DDR.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > drivers/edac/synopsys_edac.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> > index 1b630f0be119..3a1db34a8546 100644
> > --- a/drivers/edac/synopsys_edac.c
> > +++ b/drivers/edac/synopsys_edac.c
> > @@ -521,6 +521,8 @@ static void handle_error(struct mem_ctl_info *mci,
> struct synps_ecc_status *p)
> > memset(p, 0, sizeof(*p));
> > }
> >
> > +static void enable_intr(struct synps_edac_priv *priv);
> > +
> > /**
> > * intr_handler - Interrupt Handler for ECC interrupts.
> > * @irq: IRQ number.
> > @@ -562,6 +564,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
> > /* v3.0 of the controller does not have this register */
> > if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
> > writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
> > + else
> > + enable_intr(priv);
>
> nit: newline here would be good.
Hi Michal, thanks for your comments, I will add the newline here in V2.
Best regards
Sherry
>
> > return IRQ_HANDLED;
> > }
> >
>
> Acked-by: Michal Simek <michal.simek@xilinx.com>
>
> Thanks,
> Michal
next prev parent reply other threads:[~2022-04-20 6:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-18 11:17 [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver Sherry Sun
2022-03-18 11:17 ` [PATCH 1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR Sherry Sun
2022-04-20 5:56 ` Michal Simek
2022-03-18 11:17 ` [PATCH 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler " Sherry Sun
2022-04-20 5:57 ` Michal Simek
2022-04-20 6:23 ` Sherry Sun [this message]
2022-03-18 11:30 ` [PATCH 0/2] fix some bugs in V3.X Synopsys EDAC DDR driver Michal Simek
2022-04-19 15:34 ` Shubhrajyoti Datta
2022-03-25 1:28 ` Sherry Sun
2022-04-18 2:27 ` Sherry Sun
2022-04-18 8:34 ` Borislav Petkov
2022-04-18 10:12 ` Sherry Sun
2022-04-18 10:20 ` Borislav Petkov
2022-04-18 10:26 ` Sherry Sun
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