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From: "Tan, Wei Chong" <wei.chong.tan@intel.com>
To: Ingo Molnar <mingo@elte.hu>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	John Stultz <johnstul@us.ibm.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Arjan van de Ven <arjan@linux.intel.com>
Subject: RE: [GIT PULL] Additional x86 fixes for 2.6.31-rc5
Date: Thu, 6 Aug 2009 07:10:00 +0800	[thread overview]
Message-ID: <B28277FD4E0F9247A3D55704C440A140D5ADEC78@pgsmsx504.gar.corp.intel.com> (raw)
In-Reply-To: <20090731195705.GA12270@elte.hu>

> Sure, we might want the error term to be even smaller, but 
> in no way does it actually invalidate any of the logic - 
> the 'tsc' reading is just a guess anyway. Also, I think 
> that the real issue isn't even an SMI - but the fact that 
> in the very last iteration of the loop, there's no 
> serializing instruction _after_ the last 'rdtsc'. So even 
> in the absense of SMI's, we do have a situation where the 
> cycle counter was read without proper serialization.
> 

Hi,

I just recall something which I cannot understand.  Earlier when we observed the wrong CPU frequency phenomenon (1666MHz being identified as 1800MHz), we use the same CPU and put them on 2 different boards.  On one board, the failure rate is high (about 1 out of every 20).  On the other, it almost never fails.
We compare the 2 boards and they are quite close to each other with one very prominent difference.  The failing board has no PS/2 port and so is using all USB keyboard/mouse while the good board uses PS/2 keyboard/mouse.
Thus, we plug in a USB keyboard on the good board and were then able produce the failure on the good board (despite at a lower failure rate, 1 out of every 100).
Does this not point to SMI?

Regards,
Wei Chong.

      parent reply	other threads:[~2009-08-05 23:10 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-07-31 18:13 [GIT PULL] Additional x86 fixes for 2.6.31-rc5 H. Peter Anvin
2009-07-31 19:45 ` Linus Torvalds
2009-07-31 19:57   ` Ingo Molnar
2009-08-01 19:28     ` Linus Torvalds
2009-08-01 19:38       ` H. Peter Anvin
2009-08-01 22:04         ` Linus Torvalds
2009-08-01 22:35           ` H. Peter Anvin
2009-08-02  1:20           ` Paul Mackerras
2009-08-02  3:52             ` H. Peter Anvin
2009-08-03  1:01               ` Tejun Heo
2009-08-03  1:14                 ` Linus Torvalds
2009-08-03  1:49       ` Tejun Heo
2009-08-03  2:14         ` Linus Torvalds
2009-08-03  5:08           ` [PATCH 1/3] x86: Add 'percpu_read_stable()' interface for cacheable accesses Tejun Heo
2009-08-03  5:13             ` H. Peter Anvin
2009-08-03  5:18               ` Tejun Heo
2009-08-03  6:04                 ` Ingo Molnar
2009-08-03  6:08                   ` H. Peter Anvin
2009-08-03  6:16                     ` Ingo Molnar
2009-08-03  7:00                       ` Ingo Molnar
2009-08-03 15:13                         ` [PATCH 1/3 UPDATED] x86, percpu: " Tejun Heo
2009-08-03  5:10           ` [PATCH 2/3] x86,percpu: fix DECLARE/DEFINE_PER_CPU_PAGE_ALIGNED() Tejun Heo
2009-08-03  5:12           ` [PATCH 3/3] x86: collect hot percpu variables into one cacheline Tejun Heo
2009-08-05  7:34     ` [GIT PULL] Additional x86 fixes for 2.6.31-rc5 Tan, Wei Chong
2009-08-05  8:06       ` Ingo Molnar
2009-08-10  0:42         ` Tan, Wei Chong
2009-08-10  9:05           ` Ingo Molnar
2009-08-10 15:32             ` Linus Torvalds
2009-08-10  9:06           ` [tip:x86/urgent] x86: Fix serialization in pit_expect_msb() tip-bot for Linus Torvalds
2009-08-10 18:01           ` tip-bot for Linus Torvalds
2009-08-05 23:10     ` Tan, Wei Chong [this message]

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