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([2600:1010:b054:ff26:3849:a65d:14d0:f668]) by smtp.gmail.com with ESMTPSA id v76sm4708855pfj.145.2018.11.29.09.35.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Nov 2018 09:35:43 -0800 (PST) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (1.0) Subject: Re: [PATCH v2 4/4] x86/static_call: Add inline static call implementation for x86-64 From: Andy Lutomirski X-Mailer: iPhone Mail (16B92) In-Reply-To: Date: Thu, 29 Nov 2018 09:35:42 -0800 Cc: Josh Poimboeuf , Peter Zijlstra , Andrew Lutomirski , the arch/x86 maintainers , Linux List Kernel Mailing , Ard Biesheuvel , Steven Rostedt , Ingo Molnar , Thomas Gleixner , mhiramat@kernel.org, jbaron@akamai.com, Jiri Kosina , David.Laight@aculab.com, bp@alien8.de, julia@ni.com, jeyu@kernel.org, Peter Anvin Content-Transfer-Encoding: quoted-printable Message-Id: References: <20181126160217.GR2113@hirez.programming.kicks-ass.net> <20181126171036.chcbmb35ygpxziub@treble> <20181126175624.bruqfbkngbucpvxr@treble> <20181126200801.GW2113@hirez.programming.kicks-ass.net> <20181126212628.4apztfazichxnt7r@treble> <20181127084330.GX2113@hirez.programming.kicks-ass.net> <20181129094210.GC2131@hirez.programming.kicks-ass.net> <20181129143853.GO2131@hirez.programming.kicks-ass.net> <20181129163342.tp5wlfcyiazwwyoh@treble> <0A629D30-ADCF-4159-9443-E5727146F65F@amacapital.net> To: Linus Torvalds Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Nov 29, 2018, at 9:29 AM, Linus Torvalds wrote: >=20 > On Thu, Nov 29, 2018 at 9:02 AM Andy Lutomirski wrot= e: >>>=20 >>> - just restart the instruction (with the suggested "ptregs->rip --") >>>=20 >>> - to avoid any "oh, we're not making progress" issues, just fix the >>> instruction yourself to be the right call, by looking it up in the >>> "what needs to be fixed" tables. >>=20 >> I thought that too. I think it deadlocks. CPU A does text_poke_bp(). CP= U B is waiting for a spinlock with IRQs off. CPU C holds the spinlock and h= its the int3. The int3 never goes away because CPU A is waiting for CPU B t= o handle the sync_core IPI. >>=20 >> Or do you think we can avoid the IPI while the int3 is there? >=20 > I'm handwaving and thinking that CPU C that hits the int3 can just fix > up the instruction directly in its own caches, and return. >=20 > Yes, it does what he "text_poke" *will* do (so now the instruction > gets rewritten _twice_), but who cares? It's idempotent. >=20 >=20 But it=E2=80=99s out of order. I=E2=80=99m not concerned about the final IPI= =E2=80=94 I=E2=80=99m concerned about the IPI after the int3 write and befo= re the int3 is removed again. If one CPU replaces 0xcc with 0xe8, another CP= U could observe that before the last couple bytes of the call target are wri= tten and observed by all CPUs.=