From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752778AbdF2R6V (ORCPT ); Thu, 29 Jun 2017 13:58:21 -0400 Received: from mail-by2nam01on0083.outbound.protection.outlook.com ([104.47.34.83]:61199 "EHLO NAM01-BY2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752786AbdF2R6L (ORCPT ); Thu, 29 Jun 2017 13:58:11 -0400 From: "Ghannam, Yazen" To: Jack Miller CC: Borislav Petkov , "linux-kernel@vger.kernel.org" , "tglx@linutronix.de" , "x86@kernel.org" Subject: RE: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0 Thread-Topic: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != thread 0 Thread-Index: AQHS76Jnbcc3gTkcckexeDxn0cm136I6AM+AgACMQICAAAKioIAAEJSAgAABQNCAAWcLgIAAGd/w Date: Thu, 29 Jun 2017 17:58:08 +0000 Message-ID: References: <20170628000630.1973-1-jack@codezen.org> <20170628092219.4df52dhwe7q3iao5@pd.tnic> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: codezen.org; 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spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Jun 2017 17:58:08.8031 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR1201MB0131 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id v5THwbFY030478 > -----Original Message----- > From: themoken@gmail.com [mailto:themoken@gmail.com] On Behalf Of > Jack Miller > Sent: Thursday, June 29, 2017 12:23 PM > To: Ghannam, Yazen > Cc: Jack Miller ; Borislav Petkov ; linux- > kernel@vger.kernel.org; tglx@linutronix.de; x86@kernel.org > Subject: Re: [PATCH] x86/mce/AMD: Fix partial SMCA bank init when CPU 0 != > thread 0 > > On Wed, Jun 28, 2017 at 1:58 PM, Ghannam, Yazen > wrote: > >> With my patch applied, I see entries like l3_cache under hardware > >> thread 0's directory (it's shifted to CPU 1, so machinecheck1). > >> Without my patch, only machinecheck0 has anything interesting in it > >> (insn_fetch, l2_cache etc.) because the init failed on CPU 1. > >> > > > > What happens with SMT off? > > I haven't been able to test with SMT off (since it's apparent that 'nosmt' > doesn't really do anything and I don't locally have a firmware option to turn it > off). > > First things first though, like Boris I'd like to know if there's a better way to > detect this master thread, other than by APIC ID. Right now I'm working on a > v2 that will remove the CPU check, let each one perform the rdmsr and only > update empty bank info. I believe this call is being serialized elsewhere (need > to check), but if I could keep this patch to a one-liner by detecting the right > thread, I'd like to. > There is a master thread per Die, so a multi-Die system will have multiple master threads. In which case, we still need to decide which master thread will populate the array. I have a solution that doesn't rely on using a specific thread. I'll send it up shortly. Thanks, Yazen