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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5fbfda6b-414e-40e9-69bf-08d787ae7569 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Dec 2019 13:46:05.8957 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Zo1kvrKHKo7ERzmOjPfnxGoYLn7dqekkST5yGFfjEopqTL2keJlvc4PmiEbvBKKIdbm4iFbdXWQ3oqpcpE4Vl/wZ8d9GtjCpwD1LYGB8L3I= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB6213 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-23_06:2019-12-23,2019-12-23 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 spamscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912230118 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org +Kishon Thanks & Regards, Yuti Amonkar > -----Original Message----- > From: Yuti Amonkar > Sent: Monday, December 23, 2019 19:11 > To: linux-kernel@vger.kernel.org; dri-devel@lists.freedesktop.org; > maxime@cerno.tech > Cc: praneeth@ti.com; tomi.valkeinen@ti.com; jsarha@ti.com; Milind Parab > ; Swapnil Kashinath Jakhade > ; Yuti Suresh Amonkar > Subject: [PATCH v2] phy: Add DisplayPort configuration options >=20 > Allow DisplayPort PHYs to be configured through the generic functions > through a custom structure added to the generic union. > The configuration structure is used for reconfiguration of DisplayPort PH= Ys > during link training operation. >=20 > The parameters added here are the ones defined in the DisplayPort spec 1.= 4 > which include link rate, number of lanes, voltage swing and pre-emphasis. >=20 > Signed-off-by: Yuti Amonkar > --- >=20 > This patch was a part of [1] series earlier but we think that it needs to= have a > separate attention of the reviewers. Also as both [1] & [2] are dependent= on > this patch, our sincere request to reviewers to have a faster review of t= his > patch. >=20 > [1] >=20 > https://lkml.org/lkml/2019/12/11/455 >=20 > [2] >=20 > https://patchwork.kernel.org/cover/11271191/ >=20 > include/linux/phy/phy-dp.h | 95 > ++++++++++++++++++++++++++++++++++++++++++++++ > include/linux/phy/phy.h | 4 ++ > 2 files changed, 99 insertions(+) > create mode 100644 include/linux/phy/phy-dp.h >=20 > diff --git a/include/linux/phy/phy-dp.h b/include/linux/phy/phy-dp.h new > file mode 100644 index 0000000..18cad23 > --- /dev/null > +++ b/include/linux/phy/phy-dp.h > @@ -0,0 +1,95 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (C) 2019 Cadence Design Systems Inc. > + */ > + > +#ifndef __PHY_DP_H_ > +#define __PHY_DP_H_ > + > +#include > + > +/** > + * struct phy_configure_opts_dp - DisplayPort PHY configuration set > + * > + * This structure is used to represent the configuration state of a > + * DisplayPort phy. > + */ > +struct phy_configure_opts_dp { > + /** > + * @link_rate: > + * > + * Link Rate, in Mb/s, of the main link. > + * > + * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 > Mb/s > + */ > + unsigned int link_rate; > + > + /** > + * @lanes: > + * > + * Number of active, consecutive, data lanes, starting from > + * lane 0, used for the transmissions on main link. > + * > + * Allowed values: 1, 2, 4 > + */ > + unsigned int lanes; > + > + /** > + * @voltage: > + * > + * Voltage swing levels, as specified by DisplayPort specification, > + * to be used by particular lanes. One value per lane. > + * voltage[0] is for lane 0, voltage[1] is for lane 1, etc. > + * > + * Maximum value: 3 > + */ > + unsigned int voltage[4]; > + > + /** > + * @pre: > + * > + * Pre-emphasis levels, as specified by DisplayPort specification, to b= e > + * used by particular lanes. One value per lane. > + * > + * Maximum value: 3 > + */ > + unsigned int pre[4]; > + > + /** > + * @ssc: > + * > + * Flag indicating, whether or not to enable spread-spectrum > clocking. > + * > + */ > + u8 ssc : 1; > + > + /** > + * @set_rate: > + * > + * Flag indicating, whether or not reconfigure link rate and SSC to > + * requested values. > + * > + */ > + u8 set_rate : 1; > + > + /** > + * @set_lanes: > + * > + * Flag indicating, whether or not reconfigure lane count to > + * requested value. > + * > + */ > + u8 set_lanes : 1; > + > + /** > + * @set_voltages: > + * > + * Flag indicating, whether or not reconfigure voltage swing > + * and pre-emphasis to requested values. Only lanes specified > + * by "lanes" parameter will be affected. > + * > + */ > + u8 set_voltages : 1; > +}; > + > +#endif /* __PHY_DP_H_ */ > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index > 15032f14..ba0aab5 100644 > --- a/include/linux/phy/phy.h > +++ b/include/linux/phy/phy.h > @@ -16,6 +16,7 @@ > #include > #include >=20 > +#include > #include >=20 > struct phy; > @@ -46,9 +47,12 @@ enum phy_mode { > * > * @mipi_dphy: Configuration set applicable for phys supporting > * the MIPI_DPHY phy mode. > + * @dp: Configuration set applicable for phys supporting > + * the DisplayPort protocol. > */ > union phy_configure_opts { > struct phy_configure_opts_mipi_dphy mipi_dphy; > + struct phy_configure_opts_dp dp; > }; >=20 > /** > -- > 2.7.4