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From:   Sowjanya Komatineni <skomatineni@nvidia.com>
To:     Mark Brown <broonie@kernel.org>
CC:     "thierry.reding@gmail.com" <thierry.reding@gmail.com>,
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Subject: RE: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is
 reset to its default
Thread-Topic: [PATCH V1 24/26] spi: tegra114: de-assert CS before SPI mode is
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Date:   Mon, 1 Apr 2019 18:07:45 +0000
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> On Tue, Mar 26, 2019 at 10:56:45PM -0700, Sowjanya Komatineni wrote:
> > With SW CS, during transfer completion CS is de-asserted by writing=20
> > the default command1 register value to SPI_COMMAND1 register. With=20
> > this both mode and CS state are set at the same time and if current=20
> > transfer mode is different to default SPI mode and if mode change=20
> > happens prior to CS de-assert, clock polarity can change while CS is=20
> > active before transfer finishes.
>
> This is a bug fix so I'd expect it to be much earlier in the series befor=
e any of the new features.

Thanks Mark. Will change order as per your feedback in next version of patc=
h series.

I see you have applied some patches in V1 series so should I re-send again =
those as well along with feedback changes in next version or just only the =
patches that are not applied.