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Tue, 2 Apr 2019 20:27:43 +0000 Received: from BYAPR12MB3398.namprd12.prod.outlook.com ([fe80::80de:b71d:ffd0:3d26]) by BYAPR12MB3398.namprd12.prod.outlook.com ([fe80::80de:b71d:ffd0:3d26%6]) with mapi id 15.20.1750.017; Tue, 2 Apr 2019 20:27:43 +0000 From: Sowjanya Komatineni To: Rob Herring CC: "thierry.reding@gmail.com" , Jonathan Hunter , Timo Alho , "broonie@kernel.org" , "mark.rutland@arm.com" , "Krishna Yarlagadda" , Laxman Dewangan , "linux-tegra@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-spi@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: RE: [PATCH V1 21/26] DT bindings: spi: add tx/rx clock delay SPI client properties Thread-Topic: [PATCH V1 21/26] DT bindings: spi: add tx/rx clock delay SPI client properties Thread-Index: AQHU5GII4NltLCGlVEuJ3bH7lX99LKYlUQwAgAQKOKA= Date: Tue, 2 Apr 2019 20:27:43 +0000 Message-ID: References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> <1553666207-11414-21-git-send-email-skomatineni@nvidia.com> <5ca06155.1c69fb81.60281.9b59@mx.google.com> In-Reply-To: <5ca06155.1c69fb81.60281.9b59@mx.google.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=skomatineni@nvidia.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1554236870; bh=du1QvcRlYeNf26trHju2FtTfXkskcJxbfIbkgt9x8tE=; h=X-PGP-Universal:From:To:CC:Subject:Thread-Topic:Thread-Index:Date: Message-ID:References:In-Reply-To:Accept-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-ms-office365-filtering-correlation-id: x-microsoft-antispam:x-ms-traffictypediagnostic: x-microsoft-antispam-prvs:x-forefront-prvs: x-forefront-antispam-report:received-spf: x-ms-exchange-senderadcheck:x-microsoft-antispam-message-info: MIME-Version:X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg: Content-Language:Content-Type:Content-Transfer-Encoding; b=pJsxsZLu7udkOVCX/yN+jHaW3CwR/DJwrirH7jj9wC0CHz8IglE0hDzMxPoZYMmpE 5+4ERAfMPqxQuObRVoxKYn6ND0Jfx9LjUIs1jUiqsBh1udvcBEUcu4vO3b4pLyoF+7 V+u8vUYTIsZgyUZInZZHabttBPPPzzto9W4m6yb6/5NvGI8JY9olyZ0yDHAuMEBzRc hfz+QqbLhbLpbwk7WWbvNoksTBfstXlQ1oUEQ0IqWVFrToh9oP6MiG8q+03ipAf1r6 4mTAh+qw2RbS9L9AJNxVj8oDr/G9iliYFiZDS2C9TDB0Hh2OWAt+NeLcbZwdTHzJLw Y2cr8vO3HmjkQ== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Tue, Mar 26, 2019 at 10:56:42PM -0700, Sowjanya Komatineni wrote: > > This patch adds Tegra SPI master tx and rx clock delay properties. > >=20 > > TX/RX clock delays may vary depending on the platform design trace=20 > > lengths for each client on the Tegra SPI bus. These properties helps=20 > > to tune the clock delays. > >=20 > > Signed-off-by: Sowjanya Komatineni > > --- > > .../devicetree/bindings/spi/nvidia,tegra114-spi.txt | 16 ++++++++= ++++++++ > > 1 file changed, 16 insertions(+) > > Just combine this with patch 19. > > > diff --git=20 > > a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt=20 > > b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt > > index 6167c5234b64..2b84b7b726ce 100644 > > --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt > > +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt > > @@ -29,6 +29,12 @@ spi-client device controller properties: > > - nvidia,cs-hold-clk-count: CS hold timing parameter. > > - nvidia,cs-inactive-cycles: CS inactive delay in terms of clock betwe= en > > transfers. > > +- nvidia,tx-clk-tap-delay: Delays the clock going out to the external= =20 > > +device > > + with this tap value. This property is used to tune the outgoing=20 > > +data from > > + Tegra SPI master with respect to outgoing Tegra SPI master clock. > > +- nvidia,rx-clk-tap-delay: Delays the clock coming in from the=20 > > +external device > > + with this tap value. This property is used to adjust the Tegra SPI=20 > > +master > > + clock with respect to the data from the SPI slave device. > > Are there units? What's the range of values. TX/RX Clock delays are tap counts and there is internal tap-to-tap delay. Will update to specify tap to delay correlation along with supported tap va= lues range. As per feedback from mark, will move CS timing to API implementation as the= y are not Tegra SPI specific and applicable in general. > > > =20 > > Example: > > =20 > > @@ -45,4 +51,14 @@ spi@7000d600 { > > reset-names =3D "spi"; > > dmas =3D <&apbdma 16>, <&apbdma 16>; > > dma-names =3D "rx", "tx"; > > + > > + @ { > > + ... > > + ... > > + nvidia,cs-setup-clk-count =3D <10>; > > + nvidia,cs-hold-clk-count =3D <10>; > > + nvidia,rx-clk-tap-delay =3D <0>; > > + nvidia,tx-clk-tap-delay =3D <16>; > > + ... > > + }; > > }; > > -- > > 2.7.4 > >=20