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charset="us-ascii" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548297599; bh=yEDMBaPaKnnzSvU7/DYKL8eOSmk6mqglh7HJMniyXMY=; h=X-PGP-Universal:From:To:CC:Subject:Thread-Topic:Thread-Index:Date: Message-ID:References:In-Reply-To:Accept-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:authentication-results:x-originating-ip: x-ms-publictraffictype:x-microsoft-exchange-diagnostics: x-ms-office365-filtering-correlation-id:x-microsoft-antispam: x-ms-traffictypediagnostic:x-microsoft-antispam-prvs: x-forefront-prvs:x-forefront-antispam-report:received-spf: x-ms-exchange-senderadcheck:x-microsoft-antispam-message-info: spamdiagnosticoutput:spamdiagnosticmetadata:MIME-Version: X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg: Content-Language:Content-Type:Content-Transfer-Encoding; b=kRShINm4vzkoMbse1WTZrzu4OyPlXQ5w9j3UJb7/5pliQxx6ixl6jzxgY/u/WFQ3P S0m1+8lzp0sEfLe/qAGkRS06ssJCe6Q06MCv5j8fMfDqM8d6i22yZzM5hXViwL37QP wx/muJl8idQ7YVXMQ0wlhTN+XBCYwgfBdOgXnnxfKy6BOLatDI26zjB05h6JsF5Qtd 3a3/FbHR+rAPfd61muv7M77otWI3Z1fKCA3lUYd8FBabzQQUnk8BcTrIjS+c6STBtb 57IFOFlfeQvwatDuYBSHj02lCn0ofqoxP7fX2/q/mzF75mhZkYY7r4JUfDoW1oeSxY xRbxxCbYn/ElQ== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > > This patch adds DMA support for Tegra I2C. > > In the subject: "Support" -> "support". And in the commit description per= haps add some more details about why this is useful, maybe accompany with s= ome performance numbers (if > you can come up with any) or describe why the= re's a threshold for PIO vs. DMA transfers. > > As it is, it's not immediately clear why we need or want these 400+ extra= lines of code. > > > Signed-off-by: Sowjanya Komatineni > > --- > > drivers/i2c/busses/i2c-tegra.c | 494=20 > > +++++++++++++++++++++++++++++++++++++---- > > 1 file changed, 456 insertions(+), 38 deletions(-) > >=20 > > > > @@ -658,7 +809,16 @@ static irqreturn_t tegra_i2c_isr(int irq, void *de= v_id) > > if (i2c_dev->is_dvc) > > dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS); > > =20 > > - if (status & I2C_INT_PACKET_XFER_COMPLETE) { > > + if (status & I2C_INT_ALL_PACKETS_XFER_COMPLETE) { > > + if (i2c_dev->is_curr_dma_xfer) > > + i2c_dev->msg_buf_remaining =3D 0; > > Why are we forcing msg_buf_remaining to 0 here and below? Doesn't the res= t of the code take care of that already? Is it always guaranteed that all b= ytes will have been transferred in > DMA mode? During the write (Memory to TX FIFO thru DMA), DMA completion happens prior= to XFER_PACKET_COMPLETE INT from I2C During the read (RX_FIFO to Memory thru DMA), XFER_PACKET_COMPLETE I2C INT = gets generated prior to DMA Completion Receiving XFER_PACKET_COMPLETE interrupts from I2C confirms successful I2C = transfer, so In DMA Mode, msg_buf_remaining is forced to 0 DMA callback notification happens only on successful transfer of all bytes. In case of incomplete transfer by DMA, call back notification will not be g= enerated and DMA timeouts. Also, DMA timeout is verified prior to msg_complete timeout. =20 Thanks Sowjanya