From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752616AbbKBIDC (ORCPT ); Mon, 2 Nov 2015 03:03:02 -0500 Received: from smtprelay.synopsys.com ([198.182.47.9]:46061 "EHLO smtprelay.synopsys.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752053AbbKBIDA convert rfc822-to-8bit (ORCPT ); Mon, 2 Nov 2015 03:03:00 -0500 From: Vineet Gupta To: Noam Camus , "linux-snps-arc@lists.infradead.org" CC: "gilf@ezchip.com" , Peter Zijlstra , "talz@ezchip.com" , "linux-kernel@vger.kernel.org" , "cmetcalf@ezchip.com" Subject: Re: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers Thread-Topic: [PATCH v1 14/20] ARC: [plat-eznps] Use dedicated SMP barriers Thread-Index: AQHRE98q9tMDxHG3mUysr+2w15HiMQ== Date: Mon, 2 Nov 2015 08:02:56 +0000 Message-ID: References: <1446297327-16298-1-git-send-email-noamc@ezchip.com> <1446297327-16298-15-git-send-email-noamc@ezchip.com> Accept-Language: en-US, en-IN Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.12.197.182] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Saturday 31 October 2015 06:52 PM, Noam Camus wrote: > From: Noam Camus > > NPS device got 256 cores and each got 16 HW threads (SMT). > We use EZchip dedicated ISA to trigger HW scheduler of the > core that current HW thread belongs to. > This scheduling makes sure that data beyond barrier is available > to all HW threads in core and by that to all in device (4K). > > Signed-off-by: Noam Camus > Cc: Peter Zijlstra > --- > arch/arc/include/asm/barrier.h | 8 ++++++++ > 1 files changed, 8 insertions(+), 0 deletions(-) > > diff --git a/arch/arc/include/asm/barrier.h b/arch/arc/include/asm/barrier.h > index a720998..c8229b8 100644 > --- a/arch/arc/include/asm/barrier.h > +++ b/arch/arc/include/asm/barrier.h > @@ -34,6 +34,12 @@ > > #ifdef CONFIG_ISA_ARCOMPACT > > +#ifdef CONFIG_ARC_PLAT_EZNPS > +#include > +#define mb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory") > +#define rmb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory") Do u need this even for mandatory barriers whose semantics are not related to SMP at all ? I think you need them only for smb_* Following is a good introduction to difference between the two ! https://community.arm.com/groups/processors/blog/2011/04/11/memory-access-ordering-part-2--barriers-and-the-linux-kernel > +#else > + > /* > * ARCompact based cores (ARC700) only have SYNC instruction which is super > * heavy weight as it flushes the pipeline as well. > @@ -41,6 +47,8 @@ > */ > > #define mb() asm volatile("sync\n" : : : "memory") > +#endif /* CONFIG_ARC_PLAT_EZNPS */ > + > #endif > > #include