From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755255AbeDZKR6 (ORCPT ); Thu, 26 Apr 2018 06:17:58 -0400 Received: from mo4-p02-ob.smtp.rzone.de ([81.169.146.170]:14249 "EHLO mo4-p02-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754842AbeDZKRm (ORCPT ); Thu, 26 Apr 2018 06:17:42 -0400 X-RZG-AUTH: :JGIXVUS7cutRB/49FwqZ7WcJeFKiMgPgp8VKxflSZ1P34KBj4Qpw87WisdN1GTaY X-RZG-CLASS-ID: mo00 Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 9.3 \(3124\)) Subject: Re: [Letux-kernel] [PATCH v3 2/4] gpio: pca953x: add register definitions for pcal6524 and fix address calculation From: "H. Nikolaus Schaller" In-Reply-To: Date: Thu, 26 Apr 2018 12:17:23 +0200 Cc: Mark Rutland , Alexandre Courbot , Pawel Moll , Ian Campbell , Linus Walleij , kernel@pyra-handheld.com, Linux Kernel Mailing List , "open list:GPIO SUBSYSTEM" , devicetree , Rob Herring , Kumar Gala , Discussions about the Letux Kernel Message-Id: References: <0e9bea79eae7504e61fabdb4a0311f8fdc2f6b25.1523376423.git.hns@goldelico.com> <65085C47-CDA8-4F8C-8307-C145F21F7D19@goldelico.com> To: Andy Shevchenko X-Mailer: Apple Mail (2.3124) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id w3QAI3kH019720 Hi Andy, > Am 26.04.2018 um 12:06 schrieb Andy Shevchenko : > > On Wed, Apr 25, 2018 at 9:05 PM, H. Nikolaus Schaller wrote: >>> Am 11.04.2018 um 07:00 schrieb H. Nikolaus Schaller : >>>> Am 10.04.2018 um 20:06 schrieb Andy Shevchenko : >>>> On Tue, Apr 10, 2018 at 7:07 PM, H. Nikolaus Schaller wrote: > >>>>> PCAL chips ("L" seems to stand for "latched") have additional >>>>> registers starting at address 0x40 to control the latches, >>>>> interrupt mask, pull-up and pull down etc. >>>>> >>>>> The constants are so far defined in a way that they fit for >>>>> the pcal9555a when shifted by the number of banks, i.e. multiplied >>>>> by 2. >>>>> >>>>> Now the pcal6524 has 3 banks which means the relative offset >>>>> must be multiplied by 4 which gives a wrong result if not done >>>>> carefully, since the base offset is already included in the offset. >>>>> >>>>> For the basic registers shared with all pca93xx/tca64xx chips >>>>> there is no such offset. >>>>> >>>>> Therefore, we add code to adjust the register number for exended >>>>> registers to the 24 bit accessor functions. >>>>> >>>>> And we add additional register offset constants (not yet used by >>>>> the driver code) which are specific to the pcal6524. > >>>> First of all, as I said, please split this to two patches. Don't mix the things. >>> Ok. Queued for v4. > > I actually think it would be even more patches: > - move to hex from dec > - add new definitions for PCAL953x > - append new code for registers (see below) > - add definitions for PCAL6524 It is already done in my local git, just waiting for the address thing... > >>>>> + /* adjust register address for pcal6524 */ >>>>> + if (reg >= PCAL953X_OUT_STRENGTH) >>>>> + reg -= PCAL953X_OUT_STRENGTH >> 1; >>>>> + >>>> >>>> Give me some days to think about it. > > So, what about something like: > > --- 8< --- 8< --- > #define PCAL953X_GPIO_MASK GENMASK(5,0) // this makes sense even for > your initial solution > > int bank_shift = fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); > int addr = (reg & PCAL953X_GPIO_MASK) << bank_shift; > int pinctrl = (reg & ~PCAL953X_GPIO_MASK) << 1; Ok! Intersting idea. Basically decomposes register bank number (pinctrl) and register offset (addr) and shifts them differently. > > return i2c_smbus_write_i2c_block_data(chip->client, > pinctrl | addr | REG_ADDR_AI, > NBANK(chip), val); > > // similar for read. Looks good. I'll test asap. BR and thanks, Nikolaus > > --- 8< --- 8< --- > > Keep in mind your solution has a bug for registers starting from 0x30. > > -- > With Best Regards, > Andy Shevchenko