From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BF6AC47254 for ; Thu, 30 Apr 2020 21:17:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1BBED206C0 for ; Thu, 30 Apr 2020 21:17:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="frQcDQ4W" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727062AbgD3VR2 (ORCPT ); Thu, 30 Apr 2020 17:17:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40504 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726699AbgD3VRX (ORCPT ); Thu, 30 Apr 2020 17:17:23 -0400 Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6BE1DC035495 for ; Thu, 30 Apr 2020 14:17:23 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id x18so9057227wrq.2 for ; Thu, 30 Apr 2020 14:17:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=8WL5+R63j920S0bt22y/MPX2pfyBeTnA7YIOS7PRZKQ=; b=frQcDQ4WCQVLv5/aD12Lmk0nCBUbfuzzI+xShWJ0lmfghfmg7u5Nyib31+KLW4DWf6 emuYWTL/tu7itw/WxmjNCM6SVWPFLDFvZQ7ZVwNJ8cWZ/IQGEw25HZT3j5HnFP/80pEI bXwkKq1SaFh6ohPsp1ttXqes/+ik4IqrL5Kdo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8WL5+R63j920S0bt22y/MPX2pfyBeTnA7YIOS7PRZKQ=; b=YAvNiwlijFMe03azwyA2PNDJIp+yGh5lpkqngcrWc6ebIOYLT0nCGE1VuKDI1QnL3+ CY6JgtwTYfvQEiJrSP/5oSdyeCMD0kjGpwh9EaS7bNMPOLwgTPmoZ2HrdLJnp1mApSAr s8QvgNQi1hvfOKM7pOkijf5j3MHZtM7QQqnN1caLjQyEaL02Y04Pc4Tk4n2Vu3nLfSnK iBn1XAN53r7B+dv43uaEVIoqNGL8HEbhk92P43r66F7F7rqfoccTLCa/hCoa+vK8UGDB 5swnkwDL40He8FCxZiRpr/RyH9NV8Vfu3W3KpaYKiZDsLyXqweDLQ9dmK2WgdnvU2zKJ SQRA== X-Gm-Message-State: AGi0PuYxaduFyrBY9Vsfh/ULITcr91QatmZj+fEwpWgBN1/eViHtKZzt yiRvlbJoTFq3hfloek2RHYQwLrT+xYhEfktdWjSk8w== X-Google-Smtp-Source: APiQypIrbs9SeynjYCjcsyxd3tGq+jY5BQu3eRy4jVk1GxW92FiZ1RNN0wUrj73yIHP4rSrPXj6fVWi+Iva7Qb24Nhw= X-Received: by 2002:adf:f74f:: with SMTP id z15mr491830wrp.297.1588281441827; Thu, 30 Apr 2020 14:17:21 -0700 (PDT) MIME-Version: 1.0 References: <20200430185522.4116-5-james.quinlan@broadcom.com> <20200430204017.GA62947@bjorn-Precision-5520> In-Reply-To: <20200430204017.GA62947@bjorn-Precision-5520> From: Jim Quinlan Date: Thu, 30 Apr 2020 17:17:10 -0400 Message-ID: Subject: Re: [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default To: Bjorn Helgaas Cc: Nicolas Saenz Julienne , Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Florian Fainelli , "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" , open list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Apr 30, 2020 at 4:40 PM Bjorn Helgaas wrote: > > On Thu, Apr 30, 2020 at 02:55:22PM -0400, Jim Quinlan wrote: > > From: Jim Quinlan > > > > Some informal internal experiments has shown that the BrcmSTB ASPM L0s > > savings may introduce an undesirable noise signal on some customers' > > boards. In addition, L0s was found lacking in realized power savings, > > especially relative to the L1 ASPM component. This is BrcmSTB's > > experience and may not hold for others. At any rate, we disable L0s > > savings by default unless the DT node has the 'brcm,aspm-en-l0s' > > property. > > I assume this works by writing the PCIe Link Capabilities register, > which is read-only via the config space path used by the generic ASPM > code, so that code thinks the device doesn't support L0s at all. Correct. > > Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt includes > an "aspm-no-l0s" property. It'd be nice if this could use the same > property. I'd like to use the existing "aspm-no-l0s" but we'd really like to have it disabled by default. I'll probably switch but let me dwell on it a little. Thanks, Jim > > > Signed-off-by: Jim Quinlan > > --- > > drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++++- > > 1 file changed, 13 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > > index 2bc913c0262c..bc1d514b19e4 100644 > > --- a/drivers/pci/controller/pcie-brcmstb.c > > +++ b/drivers/pci/controller/pcie-brcmstb.c > > @@ -44,6 +44,9 @@ > > #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c > > #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff > > > > +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc > > +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 > > + > > #define PCIE_RC_DL_MDIO_ADDR 0x1100 > > #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 > > #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 > > @@ -696,7 +699,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) > > int num_out_wins = 0; > > u16 nlw, cls, lnksta; > > int i, ret; > > - u32 tmp; > > + u32 tmp, aspm_support; > > > > /* Reset the bridge */ > > brcm_pcie_bridge_sw_init_set(pcie, 1); > > @@ -806,6 +809,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) > > num_out_wins++; > > } > > > > + /* Only support ASPM L1 unless L0s is explicitly desired */ > > + aspm_support = PCIE_LINK_STATE_L1; > > + if (of_property_read_bool(pcie->np, "brcm,aspm-en-l0s")) > > + aspm_support |= PCIE_LINK_STATE_L0S; > > + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); > > + u32p_replace_bits(&tmp, aspm_support, > > + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK); > > + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); > > + > > /* > > * For config space accesses on the RC, show the right class for > > * a PCIe-PCIe bridge (the default setting is to be EP mode). > > -- > > 2.17.1 > >