From: Yehezkel Bernat <yehezkelshb@gmail.com>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
Andreas Noever <andreas.noever@gmail.com>,
Michael Jamet <michael.jamet@intel.com>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
Len Brown <lenb@kernel.org>, Lukas Wunner <lukas@wunner.de>,
Mario Limonciello <Mario.Limonciello@dell.com>,
Anthony Wong <anthony.wong@canonical.com>,
linux-acpi@vger.kernel.org
Subject: Re: [PATCH 3/8] thunderbolt: Use 32-bit writes when writing ring producer/consumer
Date: Fri, 5 Jul 2019 14:09:44 +0300 [thread overview]
Message-ID: <CA+CmpXtMBEtyh77fcrhX2BU8esiit56CWfZmey6LYEHZVUxf8A@mail.gmail.com> (raw)
In-Reply-To: <20190705095800.43534-4-mika.westerberg@linux.intel.com>
On Fri, Jul 5, 2019 at 12:58 PM Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:
>
> The register access should be using 32-bit reads/writes according to the
> datasheet. With the previous generation hardware 16-bit writes have been
> working but starting with ICL this is not the case anymore so fix
> producer/consumer register update to use correct width register address.
>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> ---
> drivers/thunderbolt/nhi.c | 26 ++++++++++++++++++++++----
> 1 file changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c
> index 27fbe62c7ddd..09242653da67 100644
> --- a/drivers/thunderbolt/nhi.c
> +++ b/drivers/thunderbolt/nhi.c
> @@ -143,9 +143,24 @@ static void __iomem *ring_options_base(struct tb_ring *ring)
> return io;
> }
>
> -static void ring_iowrite16desc(struct tb_ring *ring, u32 value, u32 offset)
> +static void ring_iowrite_prod(struct tb_ring *ring, u16 prod)
> {
> - iowrite16(value, ring_desc_base(ring) + offset);
> + u32 val;
> +
> + val = ioread32(ring_desc_base(ring) + 8);
> + val &= 0x0000ffff;
> + val |= prod << 16;
> + iowrite32(val, ring_desc_base(ring) + 8);
> +}
> +
> +static void ring_iowrite_cons(struct tb_ring *ring, u16 cons)
> +{
> + u32 val;
> +
> + val = ioread32(ring_desc_base(ring) + 8);
> + val &= 0xffff0000;
> + val |= cons;
> + iowrite32(val, ring_desc_base(ring) + 8);
> }
>
> static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset)
> @@ -197,7 +212,10 @@ static void ring_write_descriptors(struct tb_ring *ring)
> descriptor->sof = frame->sof;
> }
> ring->head = (ring->head + 1) % ring->size;
> - ring_iowrite16desc(ring, ring->head, ring->is_tx ? 10 : 8);
> + if (ring->is_tx)
> + ring_iowrite_prod(ring, ring->head);
> + else
> + ring_iowrite_cons(ring, ring->head);
Really a matter of taste, but maybe you want to consider having a single
function, with a 3rd parameter, bool is_tx.
The calls here will be unified to:
ring_iowrite(ring, ring->head, ring->is_tx);
(No condition is needed here).
The implementation uses the new parameter to decide which part of the register
to mask, reducing the code duplication (in my eyes):
val = ioread32(ring_desc_base(ring) + 8);
if (is_tx) {
val &= 0x0000ffff;
val |= value << 16;
} else {
val &= 0xffff0000;
val |= value;
}
iowrite32(val, ring_desc_base(ring) + 8);
I'm not sure if it improves the readability or makes it worse. Your call.
next prev parent reply other threads:[~2019-07-05 11:10 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-05 9:57 [PATCH 0/8] thunderbolt: Intel Ice Lake support Mika Westerberg
2019-07-05 9:57 ` [PATCH 1/8] thunderbolt: Correct path indices for PCIe tunnel Mika Westerberg
2019-07-05 9:57 ` [PATCH 2/8] thunderbolt: Move NVM upgrade support flag to struct icm Mika Westerberg
2019-07-05 10:52 ` Yehezkel Bernat
2019-07-05 10:58 ` Mika Westerberg
2019-07-09 15:11 ` Mario.Limonciello
2019-08-05 13:15 ` Mika Westerberg
2019-07-05 9:57 ` [PATCH 3/8] thunderbolt: Use 32-bit writes when writing ring producer/consumer Mika Westerberg
2019-07-05 11:09 ` Yehezkel Bernat [this message]
2019-07-05 11:24 ` Mika Westerberg
2019-07-05 16:04 ` David Laight
2019-08-07 16:13 ` Mika Westerberg
2019-08-07 16:22 ` David Laight
2019-08-07 16:36 ` 'Mika Westerberg'
2019-08-07 16:41 ` David Laight
2019-08-08 9:57 ` 'Mika Westerberg'
2019-08-12 9:01 ` David Laight
2019-07-05 9:57 ` [PATCH 4/8] thunderbolt: Do not fail adding switch if some port is not implemented Mika Westerberg
2019-08-03 14:14 ` Lukas Wunner
2019-08-05 13:17 ` Mika Westerberg
2019-07-05 9:57 ` [PATCH 5/8] thunderbolt: Hide switch attributes that are not set Mika Westerberg
2019-07-05 9:57 ` [PATCH 6/8] thunderbolt: Expose active parts of NVM even if upgrade is not supported Mika Westerberg
2019-07-05 9:57 ` [PATCH 7/8] thunderbolt: Add support for Intel Ice Lake Mika Westerberg
2019-07-05 14:44 ` Yehezkel Bernat
2019-07-05 14:51 ` Mika Westerberg
2019-07-05 15:02 ` Yehezkel Bernat
2019-08-04 18:25 ` Lukas Wunner
2019-08-05 14:16 ` Mika Westerberg
2019-07-05 9:58 ` [PATCH 8/8] ACPI / property: Add two new Thunderbolt property GUIDs to the list Mika Westerberg
2019-07-09 8:18 ` Rafael J. Wysocki
2019-07-05 10:33 ` [PATCH 0/8] thunderbolt: Intel Ice Lake support Mika Westerberg
2019-07-05 14:56 ` Yehezkel Bernat
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