From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755795AbcDMGUp (ORCPT ); Wed, 13 Apr 2016 02:20:45 -0400 Received: from mail-qg0-f65.google.com ([209.85.192.65]:35404 "EHLO mail-qg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933834AbcDMGUn (ORCPT ); Wed, 13 Apr 2016 02:20:43 -0400 MIME-Version: 1.0 In-Reply-To: <570CDB16.2050001@samsung.com> References: <1460091646-28701-1-git-send-email-cw00.choi@samsung.com> <1460091646-28701-6-git-send-email-cw00.choi@samsung.com> <570CDB16.2050001@samsung.com> Date: Wed, 13 Apr 2016 09:20:41 +0300 Message-ID: Subject: Re: [PATCH 5/7] clk: samsung: exynos542x: Add the clock id for ACLK From: Tomasz Figa To: Krzysztof Kozlowski Cc: Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Kukjin Kim , Sylwester Nawrocki , "Rafael J. Wysocki" , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , linux.amoon@gmail.com, m.reichl@fivetechno.de, Tobias Jakobi , InKi Dae , linux-kernel , "linux-pm@vger.kernel.org" , "linux-samsung-soc@vger.kernel.org" , linux-arm-kernel , devicetree Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2016-04-12 14:25 GMT+03:00 Krzysztof Kozlowski : > On 04/08/2016 07:00 AM, Chanwoo Choi wrote: >> This patch adds the clock id for ACLK clock which is source clock of AMBA AXI >> Bus. This clock should be handled in Bus frequency scaling driver. >> >> Signed-off-by: Chanwoo Choi >> --- >> drivers/clk/samsung/clk-exynos5420.c | 85 +++++++++++++++++++++++------------- >> 1 file changed, 55 insertions(+), 30 deletions(-) > > The IDs itself look good but you are not adding only clock ID. You are > changing all of them from NULL-flags to CLK_SET_RATE_PARENT. This should > be explained in the commit message why you need it. Probably it should > be also in separate commit. +1. And CLK_SET_RATE_PARENT for a clock which has a mux as its parent is a bit suspicious, so I'd like to know the rationale for each single clock with CLK_SET_RATE_PARENT being added. Best regards, Tomasz