From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6B73C4167B for ; Fri, 25 Nov 2022 12:52:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229536AbiKYMwJ (ORCPT ); Fri, 25 Nov 2022 07:52:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229619AbiKYMwE (ORCPT ); Fri, 25 Nov 2022 07:52:04 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1B8B1D33E; Fri, 25 Nov 2022 04:52:02 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id x2so6295402edd.2; Fri, 25 Nov 2022 04:52:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=nZM9q1K+42FsNfeDNYm/8tjXP/Kt4Gm+q17CqPvn1IU=; b=iVPArmm57/IEQXdp7tdJZqPU7TQN8yhQGrEQzHv6hpqKQFxi9oBS6DGdo0LwIZ7F9Q lBgR9+lpqH5ZuSr4N0zd5uHFNGmFw2vtBtHtTdN0738CicJC2xbL7nJbV+2KTZwXyKHj R6h9D5bEbWTPND1Vzli1NKP9AXXDYVl9V7+n7YhUmGKFzmxA2gvpKIqQhNZMRLKg+VE0 YjGzMgreZ9YHmrKiLikM5zz8NUmvMl3MBdS2NGi+/RyCfM77WeeYhbIdSXx7MqryNb/S 6PSdA52/ndBpH/TsG2taHYhax0n+0AepsOxg6VaZXkqkMlC0pU6b4aeDQJvotuCakawf qnuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=nZM9q1K+42FsNfeDNYm/8tjXP/Kt4Gm+q17CqPvn1IU=; b=msDdTNc64sI1xeuv43IiiwCi7183If1cSl2OzYRgVZWiDdS8WvpOF8Dai7hQPXwe4y vJqetm0upvzqcahL3XyNPj923mMX1exFcWLJEk1MQU+O180VVX02pDTkWgrx4sBrAB8l Dm5Ue+1t42Tm0553euehCj+TwDHGr+KuqtKG55IcbDvDt+80HkL+QF2laP0b7qG6nGLU NYVXVdLCZwPjDxD836gZqgTuSz19UWrrpItPDw1eCfrJ8ML0Zklv+qSz+ZxscdUvniYb qYEfPiw2QTELQ/L8Xwm/TNw4owhHgBGVBqjfUT301dFHkYFJk2sW6sm5qrZnUWE9b3D4 tr9g== X-Gm-Message-State: ANoB5pkjsLfsQLbkxuNBlex3kflDraynSkILeqJPjrK5RUpY3xbGkdbj mSBtddfn7OdGaL4Tk+2PwNngRllvsfPASYQcbqY= X-Google-Smtp-Source: AA0mqf5Lq4Pu7NoN/UM+TblOtprU1WDL5qvhXP3lh39E7rVRPYg6ZUFacZ1Y6gAGHGpxHM9DVnp+shoUQbO+jemouyI= X-Received: by 2002:a05:6402:1f87:b0:468:7df:c38c with SMTP id c7-20020a0564021f8700b0046807dfc38cmr34475964edc.150.1669380721124; Fri, 25 Nov 2022 04:52:01 -0800 (PST) MIME-Version: 1.0 References: <20221124172207.153718-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221124172207.153718-7-prabhakar.mahadev-lad.rj@bp.renesas.com> <70d1bfde-f57f-1741-08d3-23e362793595@linaro.org> <9b0f8312-2caa-b9f3-edf3-1b720532f559@linaro.org> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 25 Nov 2022 12:51:34 +0000 Message-ID: Subject: Re: [PATCH v4 6/7] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller To: Conor Dooley Cc: Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Guo Ren , Jisheng Zhang , Atish Patra , Anup Patel , Andrew Jones , Nathan Chancellor , Philipp Tomsich , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Conor, On Fri, Nov 25, 2022 at 12:25 PM Conor Dooley wrote: > > On Fri, Nov 25, 2022 at 01:12:18PM +0100, Krzysztof Kozlowski wrote: > > On 25/11/2022 11:34, Lad, Prabhakar wrote: > > >>> +/* Device, Non-bufferable */ > > >>> +#define AX45MP_PMACFG_MTYP_DEV_NON_BUF (0 << 2) > > >>> +/* Device, bufferable */ > > >>> +#define AX45MP_PMACFG_MTYP_DEV_BUF (1 << 2) > > >>> +/* Memory, Non-cacheable, Non-bufferable */ > > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_NON_BUF (2 << 2) > > >>> +/* Memory, Non-cacheable, Bufferable */ > > >>> +#define AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF (3 << 2) > > >> > > >> What are all these? They don't look like flags, because 3 = 1 | 2... > > >> they don't look like constants, because we do not use shifts in > > >> constants. Are these some register values? I also do not see the header > > >> being used in the code, so why having a bindings header if it is not > > >> used (DTS is not usage...)? > > >> > > > These are register bit values for the MTYP[5:2] field. The DTS example > > > in the binding doc (above) uses these macros. I haven't included the > > > DTS/I patches with this patchset yet do think I should? > > > > Then why storing it as bindings? Bindings headers describe the interface > > implemented by drivers and used by DTS, but this is not implemented by > > drivers. > > IIUC, some of these properties are non-discoverable attributes of the > cache controller. I see two things that could be done here that are > "better" than #defining bits: > - add an RZ/Five specific compatible and use match data to set the > attributes which is only possible if the pma-regions are set on a > per SoC basis > - make pma-regions into a child node, in which andestech,non-cacheable > andestech,non-bufferable etc are properties of the child node > For now the only way to get DMA working without IOCP is to have AX45MP_PMACFG_MTYP_MEM_NON_CACHE_BUF. But for future purposes I have introduced the other available flags. So maybe for now we could just have this flag andestech,mem-non-cacheable-bufferable in the binding doc. cache-controller@2010000 { reg = <0x13400000 0x100000>; compatible = "andestech,ax45mp-cache", "cache"; interrupts = <508 IRQ_TYPE_LEVEL_HIGH>; cache-line-size = <64>; cache-level = <2>; cache-sets = <1024>; cache-size = <262144>; cache-unified; andestech,pma-region@0x58000000 { reg = <0x58000000 0x08000000>; andestech,mem-non-cacheable-bufferable; }; andestech,pma-region@0xdeadbeef { reg = <0xdeadbeef 0x08000000>; andestech,mem-non-cacheable-bufferable; }; .... }; Did I chime in this time? Cheers, Prabhakar