From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 021D1C636CA for ; Fri, 16 Jul 2021 09:02:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DEEFD61357 for ; Fri, 16 Jul 2021 09:02:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239041AbhGPJFX (ORCPT ); Fri, 16 Jul 2021 05:05:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231513AbhGPJFV (ORCPT ); Fri, 16 Jul 2021 05:05:21 -0400 Received: from mail-yb1-xb34.google.com (mail-yb1-xb34.google.com [IPv6:2607:f8b0:4864:20::b34]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 53F60C06175F; Fri, 16 Jul 2021 02:02:27 -0700 (PDT) Received: by mail-yb1-xb34.google.com with SMTP id v189so13735149ybg.3; Fri, 16 Jul 2021 02:02:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cIlG7Tj9PHyebgVnc/iO72vl2A3TQGm2yNs4i4yWOOU=; b=fBRyinH2auRaW9VIjTG5wuhme+khhzh95O8QGjyGLLHSKjsDmpWtA/VF7HcPLJ9gbo 5VwU5bebcUVWTaaklRRm69PmicVKPVvjlzzohECC5oRVOJ0UbA8OGH8t3BRCDeezJgwX C9zekLGi5deY5C4huxsgPL/H9psWfPrVbGJdk5RynO542q0BRQ9PUgn8KbDt0dFNiKz1 Yxk6hCjk0csqtFYncP7l6u5jioXRB+Md9P9NINnE89OUr/XiAYfzP2HUzyxFMYrj0KLj 2sTBqouS+/m/nRj95/hyB2ZQN5vaZn3NmXIyYuI42hvBJvb5A73lkUXFNPOoG/dkWXov 1EsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cIlG7Tj9PHyebgVnc/iO72vl2A3TQGm2yNs4i4yWOOU=; b=qQy4jA3e4vhySIlwOUUNjqXeurAGW2Nos+7MCoCLbinobn6v4FJv4w7rh1ABqDATzf BArYBr0uKLeu8LB06mgjd7RiYrn+Em1ykS25gVPImZiFGHQZFao3w+VPXfD+TMiHbuMd R0Ql4aNgcrUjxlJIevPGE4FenBmUkHIymAEpbG8oIipBh+9kfUQVoPdjRuLleXqWfo+x SeAdZno1T10ENkx3fU7G3Dr7hQRVLp1ai4aFIC+cNPbR66KiFvbVaz6DgikVy78TaFUl A1JJrLGPuDZqWOSesBCOH/0uv0lqWuMJ9p5uhGbzMJtVp72TiakiU3dWT7LbNkizkaTY ep0g== X-Gm-Message-State: AOAM530jAcILAquGisPNUD19GoXVlO0yPf7Hmz5obPXvo6WS1DB+lHME pxN7xEfbnRG4NnbXqDSUnTqxYOxTK9SfV0S9ahc= X-Google-Smtp-Source: ABdhPJzjZH+UpiII0wGH5jTfkZY4AH/3/G0jav7ObOm0JDClSdgeFVXQOBQAE0iXvC9eFeyGX7vYwHMNfgK5VhLCc74= X-Received: by 2002:a25:d491:: with SMTP id m139mr11115293ybf.156.1626426146574; Fri, 16 Jul 2021 02:02:26 -0700 (PDT) MIME-Version: 1.0 References: <20210715182123.23372-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210715182123.23372-4-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 16 Jul 2021 10:02:00 +0100 Message-ID: Subject: Re: [PATCH 3/6] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock To: Geert Uytterhoeven Cc: Lad Prabhakar , Rob Herring , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Jakub Kicinski , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-can@vger.kernel.org, netdev , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-clk , Linux Kernel Mailing List , Linux-Renesas , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geert, On Fri, Jul 16, 2021 at 9:56 AM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Fri, Jul 16, 2021 at 10:45 AM Lad, Prabhakar > wrote: > > On Fri, Jul 16, 2021 at 9:08 AM Geert Uytterhoeven wrote: > > > On Thu, Jul 15, 2021 at 8:21 PM Lad Prabhakar > > > wrote: > > > > Add P0_DIV2 core clock required for CANFD module. CANFD core clock is > > > > sourced from P0_DIV2 referenced from HW manual Rev.0.50. > > > > > > OK. > > > > > > > Also add R9A07G044_LAST_CORE_CLK entry to avoid changes in > > > > r9a07g044-cpg.c file. > > > > > > I'm not so fond of adding this. Unlike the other definitions, it is > > > not really part of the bindings, but merely a convenience definition > > > for the driver. Furthermore it has to change when a new definition > > > is ever added. > > > > > Agreed will drop this. > > > > > > Signed-off-by: Lad Prabhakar > > > > Reviewed-by: Biju Das > > > > --- > > > > include/dt-bindings/clock/r9a07g044-cpg.h | 2 ++ > > > > 1 file changed, 2 insertions(+) > > > > > > > > diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h > > > > index 0728ad07ff7a..2fd20db0b2f4 100644 > > > > --- a/include/dt-bindings/clock/r9a07g044-cpg.h > > > > +++ b/include/dt-bindings/clock/r9a07g044-cpg.h > > > > @@ -30,6 +30,8 @@ > > > > #define R9A07G044_CLK_P2 19 > > > > #define R9A07G044_CLK_AT 20 > > > > #define R9A07G044_OSCCLK 21 > > > > +#define R9A07G044_CLK_P0_DIV2 22 > > > > +#define R9A07G044_LAST_CORE_CLK 23 > > > > > > Third issue: off-by-one error, it should be 22 ;-) > > > > > 23 was intentionally as these numbers aren't used for core clock count > > we use r9a07g044_core_clks[] instead. > > It ends up as an off-by-one bug in the range check in > rzg2l_cpg_clk_src_twocell_get(). > Ooops missed that! Cheers, Prabhakar > > Said that I'll drop this. > > OK. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds