From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE0ADC433F5 for ; Mon, 23 May 2022 18:03:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241646AbiEWSDY (ORCPT ); Mon, 23 May 2022 14:03:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42374 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241450AbiEWRfw (ORCPT ); Mon, 23 May 2022 13:35:52 -0400 Received: from mail-yw1-x1133.google.com (mail-yw1-x1133.google.com [IPv6:2607:f8b0:4864:20::1133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B14E87236; Mon, 23 May 2022 10:29:00 -0700 (PDT) Received: by mail-yw1-x1133.google.com with SMTP id 00721157ae682-2f83983782fso156035727b3.6; Mon, 23 May 2022 10:29:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=Pu7kA7BiPR6LthJjBkUziE8M6jqnojq51OxPzrVcphU=; b=URSiuUGoGO3JCqofa503NBbXZCppX+kd0jyfNgid7GavBJnWTdYTll2AnIYKUZIIDw KlRJJxpw0jBP/l/nHc6km/NpvKaj31rx3CIWVaIUcCnmJnSsW9ugJASugudhz6UtdQ28 +ye8S6RXSMH4S8Ojht13kQhUHt9WSFBDHqvgTti/7ZH4BQPYPpcSlv10wAOGQj19SQVj YoApnskHYU5hLpXstzqraqJ432RyS976BFs5KoCIuCQZtaII/1KzgUq4dMhvhfb79RDW H2B9SdCPToyIZn83gQBwRK1W8640K96RxgNaeIkF8VPlq4AaLeXIgoCthfJw2/YOVYZT Keuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Pu7kA7BiPR6LthJjBkUziE8M6jqnojq51OxPzrVcphU=; b=REPt84xbAu3UzZWdQBufMoHFlkuov0BTXpYA1gGOpn5UEt6kjdR8XQL4MA8H+w5DRO fz+zoSOkCXlEOwGMhAGGt4juxq20/qS6qST0YgazG18kdoNlCvsXy4lgqyUPozVTcztX VuoQQT17Wso07G8QzhhIELhcrKLy7U5n0n4pWBABR6Hicistc2uKP2nNSOrIQpXY7Nwj hfjp/xKJIjGtbbdHFWDwWEuKU158s+1v2T6nojc1J65e30Y9x1X7L5AT+0cNEBL/Nsiz O1mgcRKIQ0OWkoc90rZo6c86Phz9vYycZzX2Q4H+I4Wol5Doae85j07I4z9ePR7wbM9j 69dA== X-Gm-Message-State: AOAM533zDlNE0MxhXDCdvZmgo/xa9z/h8JSVoST395aA5CWlXOG1t/DH BUJDjzTHAEtbLw6w+pIm9IjbQD7WpMyQTbr5Cvk= X-Google-Smtp-Source: ABdhPJxDs+59pRGXFmcBcQcFS44LBGAfsQ6rdmIsiuTkv64/aRcW5tYZpKs/8vzNVZV/FX9+JakJXhsg9J3VLCScjeg= X-Received: by 2002:a0d:c101:0:b0:2ff:5824:e8a8 with SMTP id c1-20020a0dc101000000b002ff5824e8a8mr24483755ywd.413.1653326910187; Mon, 23 May 2022 10:28:30 -0700 (PDT) MIME-Version: 1.0 References: <20220518192924.20948-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Mon, 23 May 2022 18:28:04 +0100 Message-ID: Subject: Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support To: Biju Das Cc: Andy Shevchenko , Prabhakar Mahadev Lad , Marc Zyngier , Geert Uytterhoeven , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Linus Walleij , Bartosz Golaszewski , Thierry Reding , Jonathan Hunter , Bjorn Andersson , Andy Gross , Philipp Zabel , "open list:GPIO SUBSYSTEM" , linux-tegra , linux-arm-msm , devicetree , Linux Kernel Mailing List , Linux-Renesas , Phil Edworthy Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Biju, On Thu, May 19, 2022 at 7:58 AM Biju Das wrote: > > Hi Prabhakar, > > > Subject: Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support > > > > On Wed, May 18, 2022 at 10:10 PM Andy Shevchenko > > wrote: > > > > > > On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar > > > wrote: > > > > > > > > Hi All, > > > > > > > > The RZ/G2L Interrupt Controller is a front-end for the GIC found on > > > > Renesas RZ/G2L SoC's with below pins: > > > > - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI > > > > interrupts > > > > - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a > > > > maximum of only 32 can be mapped to 32 GIC SPI interrupts, > > > > - NMI edge select. > > > > > > > > > > _____________ > > > > | GIC > > | > > > > | > > ________ | > > > > ____________ | | > > | | > > > > NMI --------------------------------->| | SPI0-479 | | GIC- > > 600| | > > > > _______ | |------------>| > > | | > > > > | | | | PPI16-31 | | > > | | > > > > | | IRQ0-IRQ7 | IRQC |------------>| > > | | > > > > P0_P48_4 --->| GPIO |---------------->| | | > > |________| | > > > > | |GPIOINT0-122 | | | > > | > > > > | |---------------->| TINT0-31 | | > > | > > > > |______| |__________| > > |____________| > > > > > > > > The proposed patches add hierarchical IRQ domain, one in IRQC driver > > > > and another in pinctrl driver. Upon interrupt requests map the > > > > interrupt to GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC > > > > SPI, this mapping is handled by the pinctrl and IRQC driver. > > > > > > Where is the explanation on why valid_mask can't be used instead? > > > > > The .valid_mask option is one time setting > > One question, if it is one time setting, Is it possible to use .valid mask to invalidate > invalid gpio lines?(ie, currently gpio range is 392, but there is only 123 GPIOs > present in the SoC, not sure this call back can be used to invalidate the non-supported GPIOS??). > Yes can be added, I will include it in the next version. Cheers, Prabhakar