From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.7 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74C1DC12002 for ; Fri, 16 Jul 2021 08:46:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5AC8C610C7 for ; Fri, 16 Jul 2021 08:46:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238427AbhGPItr (ORCPT ); Fri, 16 Jul 2021 04:49:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48888 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229895AbhGPItp (ORCPT ); Fri, 16 Jul 2021 04:49:45 -0400 Received: from mail-yb1-xb31.google.com (mail-yb1-xb31.google.com [IPv6:2607:f8b0:4864:20::b31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7009C06175F; Fri, 16 Jul 2021 01:46:49 -0700 (PDT) Received: by mail-yb1-xb31.google.com with SMTP id r132so13664595yba.5; Fri, 16 Jul 2021 01:46:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=mEkDurH6BuGEH4gDwLaFvBfzHto5jjTCNrq+0Yx2I5Y=; b=AOQ1b2YZ2Y6qApxpfsoLFQ2Y5ZeVPOJyew2YyXjt3iz996WQIbZcXWFzgyqERYIUsv 6woAI+vav3GHatj0VDNQWZ6hppZmQu5o0j6gYhM4NOQChdbkkdh3zCYcc0EHJUtIrF2F TbJ362K19pzeV/vyKWKw7g+LLKWS862GMK2s2g5y26lTBNhbnpBIQs9FbI2e19GkTyB5 uOQsfG6pubrCzurrJa+oRcU1LAjynQ8MLxempdVnsQqhBeJCnZXzNDNSN2NpPIaVTwlg UDcT2L/H7loUkr1gSshSfu96TpXGrEEu8WzL6c41+dGsat0UE68fOJY9pPgq9+ia3sI+ j9Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=mEkDurH6BuGEH4gDwLaFvBfzHto5jjTCNrq+0Yx2I5Y=; b=hk+J9LcDzoSGYwX1HOnVBZEQ29AegjS53ziP4OOzAWuNSWvPYjEzVM7vdsBK/j/9+v jBv8q9j29qj8WIEgdIIa4hvAAo4aJwKc35ar1zW3sAwaK7RW0CdhAU8l6B0Yof812KFj rJiMDJb8jtbkoQm9FGngV1Ba9Cd8BDUpV6xv9MlsO2IjIoia1gsT5pYXzM97Gdsi0UAo nTlWFev50V0agmXyjaFenEFhv8mvyb+tfUui4hXItAiHpfHywi7zh214WKYl1DOatcqw 2PMBak60AyToST0fia4TNkk5vTrp8vUJyiWntX0SUYQEfvK4eOkMyg245yUyZHvIwL4W nm3w== X-Gm-Message-State: AOAM531lawMV06OSAa3T3Fd0hEvpwciwlKDnUDLhTZCAJtac7lVF7bIR YjRvtvm4ThpYEpSZlVosf9Wt5tgF+qrVc4a8I/s= X-Google-Smtp-Source: ABdhPJwEwBc5l1454QguN3MLGOEdfBsfoKJW2Mu3HRNqW5pslfSVZKQ//QhrJvF0EX1e7HbxaYcojI0eYjHoip5G3uQ= X-Received: by 2002:a25:cc52:: with SMTP id l79mr11280859ybf.476.1626425209092; Fri, 16 Jul 2021 01:46:49 -0700 (PDT) MIME-Version: 1.0 References: <20210715182123.23372-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210715182123.23372-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 16 Jul 2021 09:46:23 +0100 Message-ID: Subject: Re: [PATCH 4/6] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0_DIV2 To: Geert Uytterhoeven Cc: Lad Prabhakar , Rob Herring , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Jakub Kicinski , Michael Turquette , Stephen Boyd , Philipp Zabel , linux-can@vger.kernel.org, netdev , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-clk , Linux Kernel Mailing List , Linux-Renesas , Biju Das Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geert, Thank you for the review. On Fri, Jul 16, 2021 at 9:09 AM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Thu, Jul 15, 2021 at 8:21 PM Lad Prabhakar > wrote: > > Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK > > to R9A07G044_LAST_CORE_CLK. > > > > Signed-off-by: Lad Prabhakar > > Reviewed-by: Biju Das > > Thanks for your patch! > > > --- a/drivers/clk/renesas/r9a07g044-cpg.c > > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > > @@ -16,7 +16,7 @@ > > > > enum clk_ids { > > /* Core Clock Outputs exported to DT */ > > - LAST_DT_CORE_CLK = R9A07G044_OSCCLK, > > + LAST_DT_CORE_CLK = R9A07G044_LAST_CORE_CLK, > > Please use R9A07G044_CLK_P0_DIV2 instead. > Ok, I will update it. Cheers, Prabhakar > > > > /* External Input Clocks */ > > CLK_EXTAL, > > @@ -77,6 +77,7 @@ static const struct cpg_core_clk r9a07g044_core_clks[] __initconst = { > > DEF_FIXED("I", R9A07G044_CLK_I, CLK_PLL1, 1, 1), > > DEF_DIV("P0", R9A07G044_CLK_P0, CLK_PLL2_DIV16, DIVPL2A, > > dtable_1_32, CLK_DIVIDER_HIWORD_MASK), > > + DEF_FIXED("P0_DIV2", R9A07G044_CLK_P0_DIV2, R9A07G044_CLK_P0, 1, 2), > > DEF_FIXED("TSU", R9A07G044_CLK_TSU, CLK_PLL2_DIV20, 1, 1), > > DEF_DIV("P1", R9A07G044_CLK_P1, CLK_PLL3_DIV2_4, > > DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK), > > The rest looks good to me. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds