From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E523ECAAD3 for ; Thu, 1 Sep 2022 07:29:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233735AbiIAH3k (ORCPT ); Thu, 1 Sep 2022 03:29:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47788 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233934AbiIAH2c (ORCPT ); Thu, 1 Sep 2022 03:28:32 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4716412CB11 for ; Thu, 1 Sep 2022 00:26:22 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id b16so13482419wru.7 for ; Thu, 01 Sep 2022 00:26:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date; bh=6URCR0Wpeb5bQwy5urRdO0hju2iSMx2+jAWiT1nTtYU=; b=i9ZaVzgL8K3GGHTwz2QyJmc8n7L7qiM/bBnfx/nSkWGefaZQ4zA/eCl/SUs++RWrW+ 9kln9KIUdPPWlFXp8r53l8+ZxNmLb6Fu85zL9/ifiDdm1BBcnglO/sKPceEDzdAwhOFq 59mXVSFlC6SaaTzMEld8AvynlHJpUj6bRDvwDHazLlZhEKl9EGKh7LRhEOTiAefzSfHS u+b7bQPpe5g7XGtuSWGUUDtnWQBHGr6cPMSAsZCkvatNduKM1t9WPbaWt36CwMYL82XM Mnn5lvLYn+50F5jsJ384+PwWdxp54C9SYkscTd5A0DOC3SIKRXiLeiAgfiJrn7GtjKuN Tu5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date; bh=6URCR0Wpeb5bQwy5urRdO0hju2iSMx2+jAWiT1nTtYU=; b=QsloGWtscKxlk62TXKy0h8MLL4t4xbIwnApaHZpedKefIzg4i/PElW1Tcu3uW8rV0C ryjupEBwQ5VTv7FAOilpszN/4AeZbZ3ITJ0t/h4rhsGID0Plb9bDRGZVdExAky6NTWlj tEyD/yKG1MMemMC9vMGCVYazCS/CCrSgo1ovzWAwVQNJwt1+MMiDoqU/TV2ywFn4P8N8 4nuTdckp0etnluaqEiOaFKvd/mvjTjZBO3meID+ROAGaEgnd0mVqLH4xbHALEfVtAdlF 7PJwSmsLmf+xhcQHmibduryrhrzkv2API7SUQxEOWxJZ2lEhUf7uy3ukEMnvbp7IAfNG 7oVA== X-Gm-Message-State: ACgBeo23oNTpmNJYfbB4ttdhhnW7xYBURR3awIae3V3wa24DRstIAvj3 o8eVBmSQnsG9nN9gYUBaxR8FXhGcmpShUt3tpSDZrQ== X-Google-Smtp-Source: AA6agR4uWYbjZlVSMUEptQVzKN0UtnQh2gv8/PRyEudCuSAsJ2mxPXVlecKHf7qG3XkS1wn1a3vxDtN4k03iipWQw0Q= X-Received: by 2002:a05:6000:1549:b0:225:652e:45d4 with SMTP id 9-20020a056000154900b00225652e45d4mr14211030wry.15.1662017179994; Thu, 01 Sep 2022 00:26:19 -0700 (PDT) MIME-Version: 1.0 References: <20220829065044.1736-1-anand@edgeble.ai> <20220829065044.1736-2-anand@edgeble.ai> In-Reply-To: From: Jagan Teki Date: Thu, 1 Sep 2022 12:56:09 +0530 Message-ID: Subject: Re: [PATCH 2/2] net: ethernet: stmicro: stmmac: dwmac-rk: Add rv1126 support To: Andrew Lunn Cc: Anand Moon , Giuseppe Cavallaro , Alexandre Torgue , Jose Abreu , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Sugar Zhang , David Wu , netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 29 Aug 2022 at 18:40, Andrew Lunn wrote: > > On Mon, Aug 29, 2022 at 06:50:42AM +0000, Anand Moon wrote: > > Rockchip RV1126 has GMAC 10/100/1000M ethernet controller > > via RGMII and RMII interfaces are configured via M0 and M1 pinmux. > > > > This patch adds rv1126 support by adding delay lines of M0 and M1 > > simultaneously. > > What does 'delay lines' mean with respect to RGMII? These are MAC receive clock delay lengths. > > The RGMII signals need a 2ns delay between the clock and the data > lines. There are three places this can happen: > > 1) In the PHY > 2) Extra long lines on the PCB > 3) In the MAC > > Generally, 1) is used, and controlled via phy-mode. A value of > PHY_INTERFACE_MODE_RGMII_ID passed to the PHY driver means it will add > these delays. > > You don't want both the MAC and the PHY adding delays. Yes, but these are specific to MAC, not related to PHY delays. Similar to what is there in other Rockchip SoC families like RK3366, 3368, 3399, 3128, but these MAC clock delay lengths are grouped based on the iomux group in RV1126. We have iomux group 0 (M0) and group 1 (M1), so the rgmii has to set these lengths irrespective of whether PHY add's or not. Thanks, Jagan.