From: Andrey Konovalov <andreyknvl@gmail.com>
To: Vincenzo Frascino <vincenzo.frascino@arm.com>
Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
kasan-dev <kasan-dev@googlegroups.com>,
Andrew Morton <akpm@linux-foundation.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Dmitry Vyukov <dvyukov@google.com>,
Andrey Ryabinin <aryabinin@virtuozzo.com>,
Alexander Potapenko <glider@google.com>,
Marco Elver <elver@google.com>,
Evgenii Stepanov <eugenis@google.com>,
Branislav Rankov <Branislav.Rankov@arm.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: Re: [PATCH 4/5] arm64: mte: Add asymmetric mode support
Date: Sun, 3 Oct 2021 19:15:37 +0200 [thread overview]
Message-ID: <CA+fCnZeW35+ZmvM6SxZSb_NAMqsK42Ds_ADVKeVkfs9MT=Aovg@mail.gmail.com> (raw)
In-Reply-To: <20210913081424.48613-5-vincenzo.frascino@arm.com>
On Mon, Sep 13, 2021 at 10:14 AM Vincenzo Frascino
<vincenzo.frascino@arm.com> wrote:
>
> MTE provides an asymmetric mode for detecting tag exceptions. In
> particular, when such a mode is present, the CPU triggers a fault
> on a tag mismatch during a load operation and asynchronously updates
> a register when a tag mismatch is detected during a store operation.
>
> Add support for MTE asymmetric mode.
>
> Note: If the CPU does not support MTE asymmetric mode the kernel falls
> back on synchronous mode which is the default for kasan=on.
>
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Andrey Konovalov <andreyknvl@gmail.com>
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
> ---
> arch/arm64/include/asm/memory.h | 1 +
> arch/arm64/include/asm/mte-kasan.h | 5 +++++
> arch/arm64/kernel/mte.c | 26 ++++++++++++++++++++++++++
> 3 files changed, 32 insertions(+)
>
> diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
> index f1745a843414..1b9a1e242612 100644
> --- a/arch/arm64/include/asm/memory.h
> +++ b/arch/arm64/include/asm/memory.h
> @@ -243,6 +243,7 @@ static inline const void *__tag_set(const void *addr, u8 tag)
> #ifdef CONFIG_KASAN_HW_TAGS
> #define arch_enable_tagging_sync() mte_enable_kernel_sync()
> #define arch_enable_tagging_async() mte_enable_kernel_async()
> +#define arch_enable_tagging_asymm() mte_enable_kernel_asymm()
> #define arch_force_async_tag_fault() mte_check_tfsr_exit()
> #define arch_get_random_tag() mte_get_random_tag()
> #define arch_get_mem_tag(addr) mte_get_mem_tag(addr)
> diff --git a/arch/arm64/include/asm/mte-kasan.h b/arch/arm64/include/asm/mte-kasan.h
> index 22420e1f8c03..478b9bcf69ad 100644
> --- a/arch/arm64/include/asm/mte-kasan.h
> +++ b/arch/arm64/include/asm/mte-kasan.h
> @@ -130,6 +130,7 @@ static inline void mte_set_mem_tag_range(void *addr, size_t size, u8 tag,
>
> void mte_enable_kernel_sync(void);
> void mte_enable_kernel_async(void);
> +void mte_enable_kernel_asymm(void);
>
> #else /* CONFIG_ARM64_MTE */
>
> @@ -161,6 +162,10 @@ static inline void mte_enable_kernel_async(void)
> {
> }
>
> +static inline void mte_enable_kernel_asymm(void)
> +{
> +}
> +
> #endif /* CONFIG_ARM64_MTE */
>
> #endif /* __ASSEMBLY__ */
> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
> index 9d314a3bad3b..ef5484ecb2da 100644
> --- a/arch/arm64/kernel/mte.c
> +++ b/arch/arm64/kernel/mte.c
> @@ -137,6 +137,32 @@ void mte_enable_kernel_async(void)
> if (!system_uses_mte_async_mode())
> static_branch_enable(&mte_async_mode);
> }
> +
> +void mte_enable_kernel_asymm(void)
> +{
> + if (cpus_have_cap(ARM64_MTE_ASYMM)) {
> + __mte_enable_kernel("asymmetric", SCTLR_ELx_TCF_ASYMM);
> +
> + /*
> + * MTE asymm mode behaves as async mode for store
> + * operations. The mode is set system wide by the
> + * first PE that executes this function.
> + *
> + * Note: If in future KASAN acquires a runtime switching
> + * mode in between sync and async, this strategy needs
> + * to be reviewed.
> + */
> + if (!system_uses_mte_async_mode())
> + static_branch_enable(&mte_async_mode);
This part is confusing: mte_async_mode gets enabled for the asymm
mode, which contradicts the comment next to the mte_async_mode
definition.
> + } else {
> + /*
> + * If the CPU does not support MTE asymmetric mode the
> + * kernel falls back on synchronous mode which is the
> + * default for kasan=on.
> + */
> + mte_enable_kernel_sync();
> + }
> +}
> #endif
>
> #ifdef CONFIG_KASAN_HW_TAGS
> --
> 2.33.0
>
next prev parent reply other threads:[~2021-10-03 17:15 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-13 8:14 [PATCH 0/5] arm64: ARMv8.7-A: MTE: Add asymm mode support Vincenzo Frascino
2021-09-13 8:14 ` [PATCH 1/5] kasan: Remove duplicate of kasan_flag_async Vincenzo Frascino
2021-09-20 15:31 ` Catalin Marinas
2021-10-03 17:12 ` Andrey Konovalov
2021-09-13 8:14 ` [PATCH 2/5] arm64: mte: Bitfield definitions for Asymm MTE Vincenzo Frascino
2021-09-20 15:31 ` Catalin Marinas
2021-09-13 8:14 ` [PATCH 3/5] arm64: mte: CPU feature detection " Vincenzo Frascino
2021-09-20 15:31 ` Catalin Marinas
2021-09-20 15:41 ` Suzuki K Poulose
2021-09-13 8:14 ` [PATCH 4/5] arm64: mte: Add asymmetric mode support Vincenzo Frascino
2021-09-20 15:31 ` Catalin Marinas
2021-10-03 17:15 ` Andrey Konovalov [this message]
2021-10-04 15:39 ` Vincenzo Frascino
2021-09-13 8:14 ` [PATCH 5/5] kasan: Extend KASAN mode kernel parameter Vincenzo Frascino
2021-09-16 10:43 ` Marco Elver
2021-09-20 7:46 ` Vincenzo Frascino
2021-10-03 17:16 ` Andrey Konovalov
2021-10-04 15:45 ` Vincenzo Frascino
2021-09-20 15:32 ` Catalin Marinas
2021-09-20 21:29 ` [PATCH 0/5] arm64: ARMv8.7-A: MTE: Add asymm mode support Peter Collingbourne
2021-09-21 7:03 ` Vincenzo Frascino
2021-09-29 15:49 ` Will Deacon
2021-10-04 15:16 ` Vincenzo Frascino
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