[PATCH v3 devicetree 0/6] DT bindings for Felix DSA switch on LS1028A

[PATCH v3 devicetree 0/6] DT bindings for Felix DSA switch on LS1028A

[Vladimir Oltean]

This series officializes the device tree bindings for the embedded
Ethernet switch on NXP LS1028A (and for the reference design board).
The driver has been in the tree since v5.4-rc6.

It also performs some DT binding changes and minor cleanup, as per
feedback received in v1 and v2:

- I've changed the DT bindings for the internal ports from "gmii" to
  "internal". This means changing the ENETC phy-mode as well, for
  uniformity. So I would like the entire series to be merged through a
  single tree, probably the devicetree one - something which David
  Miller has aggreed to, here [0].
- Disabled all Ethernet ports in the LS1028A DTSI by default, which
  means not only the newly introduced switch ports, but also RGMII
  standalone port 1.

[0]: https://lkml.org/lkml/2020/2/19/973

Claudiu Manoil (2):
  arm64: dts: fsl: ls1028a: add node for Felix switch
  arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

Vladimir Oltean (4):
  arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC
    RCIE
  arm64: dts: fsl: ls1028a: disable all enetc ports by default
  net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII
  dt-bindings: net: dsa: ocelot: document the vsc9959 core

 .../devicetree/bindings/net/dsa/ocelot.txt    | 116 ++++++++++++++++++
 .../boot/dts/freescale/fsl-ls1028a-qds.dts    |   1 +
 .../boot/dts/freescale/fsl-ls1028a-rdb.dts    |  61 ++++++++-
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  89 +++++++++++++-
 drivers/net/dsa/ocelot/felix.c                |   3 +-
 drivers/net/dsa/ocelot/felix_vsc9959.c        |   3 +-
 6 files changed, 265 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt

-- 
2.17.1

[PATCH v3 devicetree 1/6] arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC RCIE

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This specifier overrides the interrupt specifier with 3 cells from gic
(/interrupt-controller@6000000), but in fact ENETC is not an interrupt
controller, so the property is bogus.

Interrupts used by the children of the ENETC RCIE must use the full
3-cell specifier required by the GIC.

The issue has no functional consequence so there is no real reason to
port the patch to stable trees.

Fixes: 927d7f857542 ("arm64: dts: fsl: ls1028a: Add PCI IERC node and ENETC endpoints")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
---
Changes in v3:
None.

Changes in v2:
None.

 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 0bf375ec959b..dfead691e509 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -683,7 +683,6 @@
 			reg = <0x01 0xf0000000 0x0 0x100000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
-			#interrupt-cells = <1>;
 			msi-parent = <&its>;
 			device_type = "pci";
 			bus-range = <0x0 0x0>;
-- 
2.17.1

[PATCH v3 devicetree 2/6] arm64: dts: fsl: ls1028a: disable all enetc ports by default

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

There are few boards that enable all ENETC ports, so instead of having
board DTs disable them, do so in the DTSI and have the boards enable the
ports they use.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Changes in v3:
Patch is new.

 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 1 +
 arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 5 +----
 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi    | 5 +++++
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index ca409d907b36..dd69c5b821e9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -225,6 +225,7 @@
 &enetc_port1 {
 	phy-handle = <&qds_phy1>;
 	phy-connection-type = "rgmii-id";
+	status = "okay";
 };
 
 &sai1 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index afb55653850d..14efe3b06042 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -180,6 +180,7 @@
 &enetc_port0 {
 	phy-handle = <&sgmii_phy0>;
 	phy-connection-type = "sgmii";
+	status = "okay";
 
 	mdio {
 		#address-cells = <1>;
@@ -190,10 +191,6 @@
 	};
 };
 
-&enetc_port1 {
-	status = "disabled";
-};
-
 &sai4 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index dfead691e509..1b330b7cce62 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -705,17 +705,22 @@
 			enetc_port0: ethernet@0,0 {
 				compatible = "fsl,enetc";
 				reg = <0x000000 0 0 0 0>;
+				status = "disabled";
 			};
+
 			enetc_port1: ethernet@0,1 {
 				compatible = "fsl,enetc";
 				reg = <0x000100 0 0 0 0>;
+				status = "disabled";
 			};
+
 			enetc_mdio_pf3: mdio@0,3 {
 				compatible = "fsl,enetc-mdio";
 				reg = <0x000300 0 0 0 0>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 			};
+
 			ethernet@0,4 {
 				compatible = "fsl,enetc-ptp";
 				reg = <0x000400 0 0 0 0>;
-- 
2.17.1

[PATCH v3 devicetree 3/6] net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

phy-mode = "gmii" is confusing because it may mean that the port
supports the 8-bit-wide parallel data interface pinout, which it
doesn't.

It may also be confusing because one of the "gmii" internal ports is
actually overclocked to run at 2.5Gbps (even though, yes, as far as the
switch MAC is concerned, it still thinks it's gigabit).

So use the phy-mode = "internal" property to describe the internal ports
inside the NXP LS1028A chip (the ones facing the ENETC). The change
should be fine, because the device tree bindings document is yet to be
introduced, and there are no stable DT blobs in use.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Michael Walle <michael@walle.cc>
---
Changes in v3:
None.

Changes in v2:
Patch is new.

 drivers/net/dsa/ocelot/felix.c         | 3 +--
 drivers/net/dsa/ocelot/felix_vsc9959.c | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c
index 3257962c147e..35124ef7e75b 100644
--- a/drivers/net/dsa/ocelot/felix.c
+++ b/drivers/net/dsa/ocelot/felix.c
@@ -176,8 +176,7 @@ static void felix_phylink_validate(struct dsa_switch *ds, int port,
 	phylink_set(mask, 100baseT_Full);
 	phylink_set(mask, 1000baseT_Full);
 
-	/* The internal ports that run at 2.5G are overclocked GMII */
-	if (state->interface == PHY_INTERFACE_MODE_GMII ||
+	if (state->interface == PHY_INTERFACE_MODE_INTERNAL ||
 	    state->interface == PHY_INTERFACE_MODE_2500BASEX ||
 	    state->interface == PHY_INTERFACE_MODE_USXGMII) {
 		phylink_set(mask, 2500baseT_Full);
diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c
index 2c812b481778..93800e81cdd4 100644
--- a/drivers/net/dsa/ocelot/felix_vsc9959.c
+++ b/drivers/net/dsa/ocelot/felix_vsc9959.c
@@ -955,8 +955,7 @@ static int vsc9959_prevalidate_phy_mode(struct ocelot *ocelot, int port,
 					phy_interface_t phy_mode)
 {
 	switch (phy_mode) {
-	case PHY_INTERFACE_MODE_GMII:
-		/* Only supported on internal to-CPU ports */
+	case PHY_INTERFACE_MODE_INTERNAL:
 		if (port != 4 && port != 5)
 			return -ENOTSUPP;
 		return 0;
-- 
2.17.1

[PATCH v3 devicetree 4/6] dt-bindings: net: dsa: ocelot: document the vsc9959 core

[Vladimir Oltean]

From: Vladimir Oltean <vladimir.oltean@nxp.com>

This patch adds the required documentation for the embedded L2 switch
inside the NXP LS1028A chip.

I've submitted it in the legacy format instead of yaml schema, because
DSA itself has not yet been converted to yaml, and this driver defines
no custom bindings.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v3:
- Clarify the real restriction regarding enetc_port2 which can't be
  disabled.
- Document the supported phy-modes on Felix switch ports.

Changes in v2:
Adapted phy-mode = "gmii" to phy-mode = "internal".

 .../devicetree/bindings/net/dsa/ocelot.txt    | 116 ++++++++++++++++++
 1 file changed, 116 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt

diff --git a/Documentation/devicetree/bindings/net/dsa/ocelot.txt b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
new file mode 100644
index 000000000000..66a129fea705
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
@@ -0,0 +1,116 @@
+Microchip Ocelot switch driver family
+=====================================
+
+Felix
+-----
+
+The VSC9959 core is currently the only switch supported by the driver, and is
+found in the NXP LS1028A. It is a PCI device, part of the larger ENETC root
+complex. As a result, the ethernet-switch node is a sub-node of the PCIe root
+complex node and its "reg" property conforms to the parent node bindings:
+
+* reg: Specifies PCIe Device Number and Function Number of the endpoint device,
+  in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).
+
+It does not require a "compatible" string.
+
+The interrupt line is used to signal availability of PTP TX timestamps and for
+TSN frame preemption.
+
+For the external switch ports, depending on board configuration, "phy-mode" and
+"phy-handle" are populated by board specific device tree instances. Ports 4 and
+5 are fixed as internal ports in the NXP LS1028A instantiation.
+
+The CPU port property ("ethernet") configures the feature called "NPI port" in
+the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are
+connected, in the Node Processor Interface (NPI) mode, to an Ethernet port.
+By default, in fsl-ls1028a.dtsi, the NPI port is assigned to the internal
+2.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific
+use case.  Moving the NPI port to an external switch port is hardware possible,
+but there is no platform support for the Linux system on the LS1028A chip to
+operate as an entire slave DSA chip.  NPI functionality (and therefore DSA
+tagging) is supported on a single port at a time.
+
+Any port can be disabled (and in fsl-ls1028a.dtsi, they are indeed all disabled
+by default, and should be enabled on a per-board basis). But if any external
+switch port is enabled at all, the ENETC PF2 (enetc_port2) should be enabled as
+well, regardless of whether it is configured as the DSA master or not. This is
+because the Felix PHYLINK implementation accesses the MAC PCS registers, which
+in hardware truly belong to the ENETC port #2 and not to Felix.
+
+Supported PHY interface types (appropriate SerDes protocol setting changes are
+needed in the RCW binary):
+
+* phy_mode = "internal": on ports 4 and 5
+* phy_mode = "sgmii": on ports 0, 1, 2, 3
+* phy_mode = "qsgmii": on ports 0, 1, 2, 3
+* phy_mode = "usxgmii": on ports 0, 1, 2, 3
+* phy_mode = "2500base-x": on ports 0, 1, 2, 3
+
+For the rest of the device tree binding definitions, which are standard DSA and
+PCI, refer to the following documents:
+
+Documentation/devicetree/bindings/net/dsa/dsa.txt
+Documentation/devicetree/bindings/pci/pci.txt
+
+Example:
+
+&soc {
+	pcie@1f0000000 { /* Integrated Endpoint Root Complex */
+		ethernet-switch@0,5 {
+			reg = <0x000500 0 0 0 0>;
+			/* IEP INT_B */
+			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				/* External ports */
+				port@0 {
+					reg = <0>;
+					label = "swp0";
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "swp1";
+				};
+
+				port@2 {
+					reg = <2>;
+					label = "swp2";
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "swp3";
+				};
+
+				/* Tagging CPU port */
+				port@4 {
+					reg = <4>;
+					ethernet = <&enetc_port2>;
+					phy-mode = "internal";
+
+					fixed-link {
+						speed = <2500>;
+						full-duplex;
+					};
+				};
+
+				/* Non-tagging CPU port */
+				port@5 {
+					reg = <5>;
+					phy-mode = "internal";
+					status = "disabled";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+	};
+};
-- 
2.17.1

[PATCH v3 devicetree 5/6] arm64: dts: fsl: ls1028a: add node for Felix switch

[Vladimir Oltean]

From: Claudiu Manoil <claudiu.manoil@nxp.com>

Add the switch device node, available on PF5, so that the switch port
sub-nodes (net devices) can be linked to corresponding board specific
phy nodes (external ports) or have their link mode defined (internal
ports).

The switch device features 6 ports, 4 with external links and 2
internally facing to the LS1028A SoC and connected via fixed links to 2
internal ENETC Ethernet controller ports.

Add the corresponding ENETC host port device nodes, mapped to PF2 and
PF6 PCIe functions. Since the switch only supports tagging on one CPU
port, only one port pair (swp4, eno2) is enabled by default and the
other, lower speed, port pair is disabled to prevent the PCI core from
probing them. If enabled, swp5 will be a fixed-link slave port.

DSA tagging can also be moved from the swp4-eno2 2.5G port pair to the
1G swp5-eno3 pair by changing the ethernet = <&enetc_port2> phandle to
<&enetc_port3> and moving it under port5, but in that case enetc_port2
should not be disabled, because it is the hardware owner of the Felix
PCS and disabling its memory would result in access faults in the Felix
DSA driver.

All ports are disabled by default, including the CPU port, and need to
be enabled on a per-board basis.

The phy-mode binding of the internal ENETC ports was modified from
"gmii" to "internal" to match the phy-mode of the internal-facing switch
ports connected to them. The ENETC driver does not perform any phy_mode
validation anyway, so the change is only cosmetic. Also, enetc_port2 is
defined as a fixed-link 1000 Mbps port even though it is 2500 Mbps (as
can be seen by the fact that it is connected to mscc_felix_port4). The
fact that it is currently defined as 1000 Mbps is an artifact of its
PHYLIB implementation instead of PHYLINK (the former can't describe a
fixed-link speed higher than what swphy can emulate from the Clause 22
MDIO spec).

The switch's INTB interrupt line signals:
- PTP TX timestamp availability
- TSN Frame Preemption

And don't forget to enable the 4MB BAR4 in the root complex ECAM space,
where the switch registers are mapped.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
---
Changes in v3:
- Disabled the CPU port and the DSA master by default.
- Removed the "ethernet" property from the DTSI to let the board set the
  CPU port.

Changes in v2:
Adapted phy-mode = "gmii" to phy-mode = "internal".

 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 83 ++++++++++++++++++-
 1 file changed, 82 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 1b330b7cce62..90ff75547db0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -700,7 +700,9 @@
 				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */
 				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
 				  /* PF1: VF0-1 BAR2 - prefetchable memory */
-				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000>;
+				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000
+				  /* BAR4 (PF5) - non-prefetchable memory */
+				  0x82000000 0x0 0x00000000  0x1 0xfc000000  0x0 0x400000>;
 
 			enetc_port0: ethernet@0,0 {
 				compatible = "fsl,enetc";
@@ -714,6 +716,18 @@
 				status = "disabled";
 			};
 
+			enetc_port2: ethernet@0,2 {
+				compatible = "fsl,enetc";
+				reg = <0x000200 0 0 0 0>;
+				phy-mode = "internal";
+				status = "disabled";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
 			enetc_mdio_pf3: mdio@0,3 {
 				compatible = "fsl,enetc-mdio";
 				reg = <0x000300 0 0 0 0>;
@@ -727,6 +741,73 @@
 				clocks = <&clockgen 4 0>;
 				little-endian;
 			};
+
+			ethernet-switch@0,5 {
+				reg = <0x000500 0 0 0 0>;
+				/* IEP INT_B */
+				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					/* External ports */
+					mscc_felix_port0: port@0 {
+						reg = <0>;
+						status = "disabled";
+					};
+
+					mscc_felix_port1: port@1 {
+						reg = <1>;
+						status = "disabled";
+					};
+
+					mscc_felix_port2: port@2 {
+						reg = <2>;
+						status = "disabled";
+					};
+
+					mscc_felix_port3: port@3 {
+						reg = <3>;
+						status = "disabled";
+					};
+
+					/* Internal ports */
+					mscc_felix_port4: port@4 {
+						reg = <4>;
+						phy-mode = "internal";
+						status = "disabled";
+
+						fixed-link {
+							speed = <2500>;
+							full-duplex;
+						};
+					};
+
+					mscc_felix_port5: port@5 {
+						reg = <5>;
+						phy-mode = "internal";
+						status = "disabled";
+
+						fixed-link {
+							speed = <1000>;
+							full-duplex;
+						};
+					};
+				};
+			};
+
+			enetc_port3: ethernet@0,6 {
+				compatible = "fsl,enetc";
+				reg = <0x000600 0 0 0 0>;
+				phy-mode = "internal";
+				status = "disabled";
+
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
 		};
 	};
 
-- 
2.17.1

[PATCH v3 devicetree 6/6] arm64: dts: fsl: ls1028a: enable switch PHYs on RDB

[Vladimir Oltean]

From: Claudiu Manoil <claudiu.manoil@nxp.com>

Link the switch PHY nodes to the central MDIO controller PCIe endpoint
node on LS1028A (implemented as PF3) so that PHYs are accessible via
MDIO.

Enable SGMII AN on the Felix PCS by telling PHYLINK that the VSC8514
quad PHY is capable of in-band-status.

The PHYs are used in poll mode due to an issue with the interrupt line
on current revisions of the LS1028A-RDB board.

Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v3:
- Set and enable the CPU port and DSA master from the board-specific
  fsl-ls1028a-rdb.dts.
- Move the "status" property to last.

Changes in v2:
None.

 .../boot/dts/freescale/fsl-ls1028a-rdb.dts    | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 14efe3b06042..6d05b76c2c7a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -177,6 +177,25 @@
 	status = "okay";
 };
 
+&enetc_mdio_pf3 {
+	/* VSC8514 QSGMII quad PHY */
+	qsgmii_phy0: ethernet-phy@10 {
+		reg = <0x10>;
+	};
+
+	qsgmii_phy1: ethernet-phy@11 {
+		reg = <0x11>;
+	};
+
+	qsgmii_phy2: ethernet-phy@12 {
+		reg = <0x12>;
+	};
+
+	qsgmii_phy3: ethernet-phy@13 {
+		reg = <0x13>;
+	};
+};
+
 &enetc_port0 {
 	phy-handle = <&sgmii_phy0>;
 	phy-connection-type = "sgmii";
@@ -191,6 +210,47 @@
 	};
 };
 
+&enetc_port2 {
+	status = "okay";
+};
+
+&mscc_felix_port0 {
+	label = "swp0";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy0>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&mscc_felix_port1 {
+	label = "swp1";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy1>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&mscc_felix_port2 {
+	label = "swp2";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy2>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&mscc_felix_port3 {
+	label = "swp3";
+	managed = "in-band-status";
+	phy-handle = <&qsgmii_phy3>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&mscc_felix_port4 {
+	ethernet = <&enetc_port2>;
+	status = "okay";
+};
+
 &sai4 {
 	status = "okay";
 };
-- 
2.17.1

Re: [PATCH v3 devicetree 0/6] DT bindings for Felix DSA switch on LS1028A

[Shawn Guo]

On Sun, Feb 23, 2020 at 10:47:10PM +0200, Vladimir Oltean wrote:
> This series officializes the device tree bindings for the embedded
> Ethernet switch on NXP LS1028A (and for the reference design board).
> The driver has been in the tree since v5.4-rc6.
> 
> It also performs some DT binding changes and minor cleanup, as per
> feedback received in v1 and v2:
> 
> - I've changed the DT bindings for the internal ports from "gmii" to
>   "internal". This means changing the ENETC phy-mode as well, for
>   uniformity. So I would like the entire series to be merged through a
>   single tree, probably the devicetree one - something which David
>   Miller has aggreed to, here [0].
> - Disabled all Ethernet ports in the LS1028A DTSI by default, which
>   means not only the newly introduced switch ports, but also RGMII
>   standalone port 1.
> 
> [0]: https://lkml.org/lkml/2020/2/19/973
> 
> Claudiu Manoil (2):
>   arm64: dts: fsl: ls1028a: add node for Felix switch
>   arm64: dts: fsl: ls1028a: enable switch PHYs on RDB
> 
> Vladimir Oltean (4):
>   arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for ENETC
>     RCIE
>   arm64: dts: fsl: ls1028a: disable all enetc ports by default

I applied these 4 DTS patches with changing prefix to 'arm64: dts: ls1028a: '.

Shawn

>   net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII
>   dt-bindings: net: dsa: ocelot: document the vsc9959 core
> 
>  .../devicetree/bindings/net/dsa/ocelot.txt    | 116 ++++++++++++++++++
>  .../boot/dts/freescale/fsl-ls1028a-qds.dts    |   1 +
>  .../boot/dts/freescale/fsl-ls1028a-rdb.dts    |  61 ++++++++-
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  89 +++++++++++++-
>  drivers/net/dsa/ocelot/felix.c                |   3 +-
>  drivers/net/dsa/ocelot/felix_vsc9959.c        |   3 +-
>  6 files changed, 265 insertions(+), 8 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/net/dsa/ocelot.txt
> 
> -- 
> 2.17.1
> 

Re: [PATCH v3 devicetree 0/6] DT bindings for Felix DSA switch on LS1028A

[Michael Walle]

Hi Shawn,

Am 2020-02-24 12:20, schrieb Shawn Guo:
> On Sun, Feb 23, 2020 at 10:47:10PM +0200, Vladimir Oltean wrote:
>> This series officializes the device tree bindings for the embedded
>> Ethernet switch on NXP LS1028A (and for the reference design board).
>> The driver has been in the tree since v5.4-rc6.
>> 
>> It also performs some DT binding changes and minor cleanup, as per
>> feedback received in v1 and v2:
>> 
>> - I've changed the DT bindings for the internal ports from "gmii" to
>>   "internal". This means changing the ENETC phy-mode as well, for
>>   uniformity. So I would like the entire series to be merged through a
>>   single tree, probably the devicetree one - something which David
>>   Miller has aggreed to, here [0].
>> - Disabled all Ethernet ports in the LS1028A DTSI by default, which
>>   means not only the newly introduced switch ports, but also RGMII
>>   standalone port 1.
>> 
>> [0]: https://lkml.org/lkml/2020/2/19/973
>> 
>> Claudiu Manoil (2):
>>   arm64: dts: fsl: ls1028a: add node for Felix switch
>>   arm64: dts: fsl: ls1028a: enable switch PHYs on RDB
>> 
>> Vladimir Oltean (4):
>>   arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for 
>> ENETC
>>     RCIE
>>   arm64: dts: fsl: ls1028a: disable all enetc ports by default
> 
> I applied these 4 DTS patches with changing prefix to 'arm64: dts: 
> ls1028a: '.

Oh, then the kontron-sl28 boards won't have ethernet because the nodes 
are
disabled now. I'll send a patch shortly which explicitly sets the status 
to
"okay", hopefully you can pick it up so it'll end up in the same pull 
request
as this one:

   arm64: dts: fsl: ls1028a: disable all enetc ports by default

-michael

> 
> Shawn
> 
>>   net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII
>>   dt-bindings: net: dsa: ocelot: document the vsc9959 core
>> 
>>  .../devicetree/bindings/net/dsa/ocelot.txt    | 116 
>> ++++++++++++++++++
>>  .../boot/dts/freescale/fsl-ls1028a-qds.dts    |   1 +
>>  .../boot/dts/freescale/fsl-ls1028a-rdb.dts    |  61 ++++++++-
>>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  89 +++++++++++++-
>>  drivers/net/dsa/ocelot/felix.c                |   3 +-
>>  drivers/net/dsa/ocelot/felix_vsc9959.c        |   3 +-
>>  6 files changed, 265 insertions(+), 8 deletions(-)
>>  create mode 100644 
>> Documentation/devicetree/bindings/net/dsa/ocelot.txt
>> 
>> --
>> 2.17.1
>> 

Re: [PATCH v3 devicetree 0/6] DT bindings for Felix DSA switch on LS1028A

[Vladimir Oltean]

Hi Michael,

On Mon, 24 Feb 2020 at 13:38, Michael Walle <michael@walle.cc> wrote:
>
> Hi Shawn,
>
> Am 2020-02-24 12:20, schrieb Shawn Guo:
> > On Sun, Feb 23, 2020 at 10:47:10PM +0200, Vladimir Oltean wrote:
> >> This series officializes the device tree bindings for the embedded
> >> Ethernet switch on NXP LS1028A (and for the reference design board).
> >> The driver has been in the tree since v5.4-rc6.
> >>
> >> It also performs some DT binding changes and minor cleanup, as per
> >> feedback received in v1 and v2:
> >>
> >> - I've changed the DT bindings for the internal ports from "gmii" to
> >>   "internal". This means changing the ENETC phy-mode as well, for
> >>   uniformity. So I would like the entire series to be merged through a
> >>   single tree, probably the devicetree one - something which David
> >>   Miller has aggreed to, here [0].
> >> - Disabled all Ethernet ports in the LS1028A DTSI by default, which
> >>   means not only the newly introduced switch ports, but also RGMII
> >>   standalone port 1.
> >>
> >> [0]: https://lkml.org/lkml/2020/2/19/973
> >>
> >> Claudiu Manoil (2):
> >>   arm64: dts: fsl: ls1028a: add node for Felix switch
> >>   arm64: dts: fsl: ls1028a: enable switch PHYs on RDB
> >>
> >> Vladimir Oltean (4):
> >>   arm64: dts: fsl: ls1028a: delete extraneous #interrupt-cells for
> >> ENETC
> >>     RCIE
> >>   arm64: dts: fsl: ls1028a: disable all enetc ports by default
> >
> > I applied these 4 DTS patches with changing prefix to 'arm64: dts:
> > ls1028a: '.
>
> Oh, then the kontron-sl28 boards won't have ethernet because the nodes
> are
> disabled now. I'll send a patch shortly which explicitly sets the status
> to
> "okay", hopefully you can pick it up so it'll end up in the same pull
> request
> as this one:
>
>    arm64: dts: fsl: ls1028a: disable all enetc ports by default
>

Sorry, I didn't notice your board.

> -michael
>
> >
> > Shawn
> >
> >>   net: dsa: felix: Use PHY_INTERFACE_MODE_INTERNAL instead of GMII
> >>   dt-bindings: net: dsa: ocelot: document the vsc9959 core
> >>
> >>  .../devicetree/bindings/net/dsa/ocelot.txt    | 116
> >> ++++++++++++++++++
> >>  .../boot/dts/freescale/fsl-ls1028a-qds.dts    |   1 +
> >>  .../boot/dts/freescale/fsl-ls1028a-rdb.dts    |  61 ++++++++-
> >>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  89 +++++++++++++-
> >>  drivers/net/dsa/ocelot/felix.c                |   3 +-
> >>  drivers/net/dsa/ocelot/felix_vsc9959.c        |   3 +-
> >>  6 files changed, 265 insertions(+), 8 deletions(-)
> >>  create mode 100644
> >> Documentation/devicetree/bindings/net/dsa/ocelot.txt
> >>
> >> --
> >> 2.17.1
> >>

Regards,
-Vladimir