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From: Alexandre Ghiti <alexandre.ghiti@canonical.com>
To: Nick Kossifidis <mick@ics.forth.gr>
Cc: "Philipp Tomsich" <philipp.tomsich@vrull.eu>,
	"Anup Patel" <anup@brainfault.org>, "Guo Ren" <guoren@kernel.org>,
	"Anup Patel" <anup.patel@wdc.com>,
	"Atish Patra" <atish.patra@wdc.com>,
	"Palmer Dabbelt" <palmerdabbelt@google.com>,
	"Christoph Müllner" <christoph.muellner@vrull.eu>,
	"Christoph Hellwig" <hch@lst.de>, liush <liush@allwinnertech.com>,
	wefu@redhat.com, "Wei Wu (吴伟)" <lazyparser@gmail.com>,
	"Drew Fustini" <drew@beagleboard.org>,
	linux-riscv <linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org List"
	<linux-kernel@vger.kernel.org>,
	taiten.peng@canonical.com,
	"Aniket Ponkshe" <aniket.ponkshe@canonical.com>,
	"Heinrich Schuchardt" <heinrich.schuchardt@canonical.com>,
	"Gordan Markus" <gordan.markus@canonical.com>,
	"Guo Ren" <guoren@linux.alibaba.com>,
	"Arnd Bergmann" <arnd@arndb.de>, "Chen-Yu Tsai" <wens@csie.org>,
	"Maxime Ripard" <maxime@cerno.tech>,
	"Daniel Lustig" <dlustig@nvidia.com>,
	"Greg Favor" <gfavor@ventanamicro.com>,
	"Andrea Mondelli" <andrea.mondelli@huawei.com>,
	"Jonathan Behrens" <behrensj@mit.edu>,
	Xinhaoqu <xinhaoqu@huawei.com>,
	"Bill Huffman" <huffman@cadence.com>,
	"Allen Baum" <allen.baum@esperantotech.com>,
	"Josh Scheid" <jscheid@ventanamicro.com>,
	"Richard Trauben" <rtrauben@gmail.com>
Subject: Re: [PATCH] riscv: Add RISC-V svpbmt extension
Date: Thu, 23 Sep 2021 13:50:52 +0200	[thread overview]
Message-ID: <CA+zEjCsO2CyhrfGGA4ceAH=LBOyqWF4U7F91VheTdr6wEJj1pw@mail.gmail.com> (raw)
In-Reply-To: <88696248a0c19a5dff660354b837514d@mailhost.ics.forth.gr>

On Thu, Sep 23, 2021 at 12:11 PM Nick Kossifidis <mick@ics.forth.gr> wrote:
>
> Στις 2021-09-23 13:04, Philipp Tomsich έγραψε:
> >
> > How if we expand this to a mmu subnode in cpu@x and add a booleans for
> > adornments like svnapot and svpbmt?
> > The older mmu-type could then treated to indicate a mmu w/o any
> > adornments specified.  I am aware that this generates an additional
> > parsing-path that will be maintained, but it will allow future
> > properties to be grouped.
> >
> > cpu@0 {
> > ...
> > mmu {
> > type = "riscv,sv39";
> > supports-svpbmt;
> > }
> > ...
> > }
>
> I was about to propose the same thing, we can do this now without
> breaking backwards compatibility, we don't really use mmu-type property
> at this point, we are either sv39 or nommu.

Indeed, this property is only informative and not useful since we can
directly "ask" the hw what it supports (cf sv48 patchset). And it
cannot actually be used to force a certain svXX since reading the
device tree happens way too late in the boot process (I have this
issue with my sv48 patchset where I used to read the device tree to
set the size of the address space, but it actually breaks KASAN).

Isn't there a way to know if it supports svPBMT at runtime?

Alex

>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2021-09-23 11:51 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-23  7:27 [PATCH] riscv: Add RISC-V svpbmt extension guoren
2021-09-23  9:13 ` Anup Patel
2021-09-23 11:53   ` Guo Ren
2021-09-23  9:24 ` Nick Kossifidis
2021-09-23  9:37   ` Anup Patel
2021-09-23  9:42     ` Nick Kossifidis
2021-09-23  9:48       ` Nick Kossifidis
2021-09-23  9:57         ` Anup Patel
2021-09-23 10:07         ` Philipp Tomsich
2021-09-23 10:36           ` Anup Patel
     [not found]         ` <CAAeLtUDu0yaDBcuC06nX1WUQC9k4eNuWjvAFrpkP_h0nf5BZAw@mail.gmail.com>
2021-09-23 10:09           ` Nick Kossifidis
2021-09-23 11:50             ` Alexandre Ghiti [this message]
2021-09-23 12:05               ` Anup Patel
2021-09-23 12:05             ` Guo Ren
2021-09-23 12:04   ` Guo Ren

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