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s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wgWT8glNh9NlJS5p0NFisrV3DtTQRZ5P1kbkf3d41QA=; b=ZPFO4XaFLpqj4VXlrBucZLydrAcmQon9KDczQQlmJcSxHExEShn+2dWDyB3W4Ei/iE uxrNGQMCoMPP7AtfegNMINUqkwyDe6VKTAd9oIUpuL6zo0EgY3Dfjk/LCtpmrU8I86YJ wik9PWbh5EbLSvHqk9mo+jKmzxYLmXM3Q51mlY86W27QXnEHJ0ybqaluOJwO17F6It5L njuYCnboS0GPNAyzEyofx+g7yWuspkOYrqTBIE7e7kXcMhp6y7tyae2U5+nK/JKIXMst 7HysKgHMeC9Ne2PxgEnNzvqfS8AOTDlIpUGC7Z2RmNJ36h70cU/uKtQZ93n5+OKpwTbW wCHA== X-Gm-Message-State: AOAM5314MCNuTRpBb93CCZF+DjSMBgHQMwBBjQZcTaS+o7kQzpmV0LyS /Udpi+XP4Td89BnL/X1i4w6B/3x9UupUFknb3fY= X-Google-Smtp-Source: ABdhPJz1gwU0uszCDNnZoynqlsVmncT7Aet0+fx1EcUJy1lbg2YOnBzrGLogRpw+jzBDLcDw+VlHcu/IAG72u0Omq+w= X-Received: by 2002:a9d:4115:: with SMTP id o21mr3237071ote.52.1621324458608; Tue, 18 May 2021 00:54:18 -0700 (PDT) MIME-Version: 1.0 References: <20210517171205.1581938-1-abelvesa@kernel.org> <20210517171205.1581938-5-abelvesa@kernel.org> In-Reply-To: <20210517171205.1581938-5-abelvesa@kernel.org> From: Dong Aisheng Date: Tue, 18 May 2021 15:53:16 +0800 Message-ID: Subject: Re: [PATCH 4/7] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi To: Abel Vesa Cc: Rob Herring , Shawn Guo , Sascha Hauer , Fabio Estevam , Jacky Bai , Dong Aisheng , NXP Linux Team , devicetree , Linux Kernel Mailing List , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Abel Vesa Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 18, 2021 at 1:15 AM wrote: > > From: Jacky Bai > > On i.MX8DXL, the Connectivity subsystem includes below peripherals: > 1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG, > 1x eMMC, 2x SD, 1x NAND. > > Signed-off-by: Jacky Bai > Signed-off-by: Abel Vesa > --- > .../boot/dts/freescale/imx8dxl-ss-conn.dtsi | 133 ++++++++++++++++++ > 1 file changed, 133 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi > new file mode 100644 > index 000000000000..c10801926de3 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi > @@ -0,0 +1,133 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2019-2021 NXP > + */ > + > +/delete-node/ &enet1_lpcg; > +/delete-node/ &fec2; > + > +&conn_subsys { > + conn_enet0_root_clk: clock-conn-enet0-root { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <250000000>; > + clock-output-names = "conn_enet0_root_clk"; > + }; > + > + eqos: ethernet@5b050000 { > + compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; > + reg = <0x5b050000 0x10000>; > + interrupt-parent = <&gic>; > + interrupts = , > + ; > + interrupt-names = "eth_wake_irq", "macirq"; > + clocks = <&eqos_lpcg 2>, > + <&eqos_lpcg 4>, > + <&eqos_lpcg 0>, > + <&eqos_lpcg 3>, > + <&eqos_lpcg 1>; need fix LPCG index pls refer to binding doc > + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; > + assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>; > + assigned-clock-rates = <125000000>; > + power-domains = <&pd IMX_SC_R_ENET_1>; > + clk_csr = <0>; > + status = "disabled"; > + }; > + > + usbotg2: usb@5b0e0000 { > + compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb"; > + reg = <0x5b0e0000 0x200>; > + interrupt-parent = <&gic>; > + interrupts = ; > + fsl,usbphy = <&usbphy2>; > + fsl,usbmisc = <&usbmisc2 0>; > + /* > + * usbotg1 and usbotg2 share one clcok > + * scfw disable clock access and keep it always on > + * in case other core (M4) use one of these. > + */ > + clocks = <&clk_dummy>; > + ahb-burst-config = <0x0>; > + tx-burst-size-dword = <0x10>; > + rx-burst-size-dword = <0x10>; > + #stream-id-cells = <1>; > + power-domains = <&pd IMX_SC_R_USB_1>; > + status = "disabled"; > + }; > + > + usbmisc2: usbmisc@5b0e0200 { > + #index-cells = <1>; > + compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc"; > + reg = <0x5b0e0200 0x200>; > + }; > + > + usbphy2: usbphy@0x5b110000 { > + compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy"; > + reg = <0x5b110000 0x1000>; > + clocks = <&usb2_2_lpcg 0>; > + status = "disabled"; > + }; > + > + eqos_lpcg: clock-controller@5b240000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x5b240000 0x10000>; > + #clock-cells = <1>; > + clocks = <&conn_enet0_root_clk>, > + <&conn_axi_clk>, > + <&conn_axi_clk>, > + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, > + <&conn_ipg_clk>; > + bit-offset = <0 8 16 20 24>; > + clock-output-names = "eqos_ptp", > + "eqos_mem_clk", > + "eqos_aclk", > + "eqos_clk", > + "eqos_csr_clk"; > + power-domains = <&pd IMX_SC_R_ENET_1>; > + }; > + > + usb2_2_lpcg: clock-controller@5b280000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x5b280000 0x10000>; > + #clock-cells = <1>; > + > + bit-offset = <28>; > + clocks = <&conn_ipg_clk>; > + clock-output-names = "usboh3_2_phy_ipg_clk"; > + }; > + > +}; > + > +&enet0_lpcg { > + clocks = <&conn_enet0_root_clk>, > + <&conn_enet0_root_clk>, > + <&conn_axi_clk>, > + <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>, > + <&conn_ipg_clk>, > + <&conn_ipg_clk>; > +}; > + > +&fec1 { > + compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec"; > + interrupts = , > + , > + , > + ; > + assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; > + assigned-clock-rates = <125000000>; > +}; > + > +&usdhc1 { > + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; > + interrupts = ; > +}; > + > +&usdhc2 { > + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; > + interrupts = ; > +}; > + > +&usdhc3 { > + compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc"; > + interrupts = ; > +}; > -- > 2.31.1 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel