From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DA2EC433ED for ; Wed, 12 May 2021 23:35:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 32C7B61412 for ; Wed, 12 May 2021 23:35:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231241AbhELXgm (ORCPT ); Wed, 12 May 2021 19:36:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376728AbhELXKM (ORCPT ); Wed, 12 May 2021 19:10:12 -0400 Received: from mail-qt1-x82e.google.com (mail-qt1-x82e.google.com [IPv6:2607:f8b0:4864:20::82e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17657C061362 for ; Wed, 12 May 2021 16:06:30 -0700 (PDT) Received: by mail-qt1-x82e.google.com with SMTP id h21so14771909qtu.5 for ; Wed, 12 May 2021 16:06:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=fSA6VzsIwmfQzLcNKI8LXXgzEauW/SKmRsgvPavPb1Q=; b=lSgJwqGGYIigKbhvNgOo5aPNIj7rMjm2SPJFubN+7K5mKdrR8GO1Rx/jKYWJGfq9fU mfRcpFg5O5xuwz+8NbUAIi8oOfNXfuIwEAe9Ec90tSZH3w4F1LQhC+PZeUn9tmlgj7t+ 3CCB0o28l3U+PQuZ6jE+ex/et0/sYpu/Y5o4RFFgqjHOx4/9zCJINGJANaQLBJqroAoZ MJ3my72/dxeWIVJNdVhzDYdeWkDdTpxo37cTQhTn7SsJgtHH8mDnkTBQgYjwira3xoGu Wg4SvmXPoNv7oAcUifXU6/Xv+t0YXcyY37NdoOT2VjUqJIadDe0IgrAAUWxSC+TcXwc0 wteA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=fSA6VzsIwmfQzLcNKI8LXXgzEauW/SKmRsgvPavPb1Q=; b=Djp+16/R3c5LaXygFroC2Rp9TJWyjImIEkNEHNL613FwO9JTh0bg4XqBUR7RrF0xBU JxanhAHkR7Ae8REscgj3FJPSMAas0Jt63RyymoiO8zzSgrDZ0k05Y0bQSsMUjIW3NwA9 z2XLxftCETx4o6THJg9kik3mS3f78VzpToFsLktduAz0lopBcG/OlI7d3o7i5ugE3oGV 3Mu5zBUaiY+oHL1exugsLxtk459xBsCvyfaMwiP5d4YNP0xUfsUZtwUeD8zIWQjHqv5d xJy+cdb8ua6IrYpvMSMSl4e1606Nc/W3R0/94tu/HxZFiPyVfEud/gsdFk3eVSTQbVXb bykA== X-Gm-Message-State: AOAM533JE4VOJQIYFIZG+Jrh5B8CYiG0ovo6gocyif6m6hbDnQz2lFZJ +A9kSTizxFoBvkw33nov62IUHN6Ub9aXamU9rH3OMQ== X-Google-Smtp-Source: ABdhPJwNY+3a9n8mvM9DQXFuQkiS1A43uoxqFXSgOGsLEv6At8EWBnkk+1fje3jZYNb2xSA8jH5nPvQV2HkOUdp/aYg= X-Received: by 2002:ac8:7d14:: with SMTP id g20mr16022130qtb.298.1620860789269; Wed, 12 May 2021 16:06:29 -0700 (PDT) MIME-Version: 1.0 References: <20210511041852.592295-1-bjorn.andersson@linaro.org> <20210511041852.592295-3-bjorn.andersson@linaro.org> In-Reply-To: <20210511041852.592295-3-bjorn.andersson@linaro.org> From: Dmitry Baryshkov Date: Thu, 13 May 2021 02:06:18 +0300 Message-ID: Subject: Re: [PATCH 2/4] drm/msm/dpu: Clear boot loader configured data paths To: Bjorn Andersson Cc: Rob Clark , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , freedreno , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 11 May 2021 at 07:18, Bjorn Andersson wrote: > > It's typical for the bootloader to configure CTL_0 for the boot splash > or EFIFB, but for non-DSI use cases the DPU driver tend to pick another > CTL and the system might end up with two configured data paths producing > data on the same INTF - with resulting graphical artifacts. > > Naturally the end goal would be to inherit the bootloader's > configuration and provide the user with a glitch free handover from the > boot configuration to a running DPU. > But such effort will affect clocks, regulators, power-domains etc, so in > the meantime this patch simply disables all INTFs and clear all > configured data paths, to avoid the graphical artifacts. Good idea. We'd have to be careful to test this with interfaces in command mode. > > Signed-off-by: Bjorn Andersson > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 4 +++ > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++ > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 36 ++++++++++++++++++++++ > drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8 +++++ > 4 files changed, 50 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 2d4645e01ebf..7aba27c1055a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -349,9 +349,13 @@ static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx) > DPU_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0); > DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0); > DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0); > + > + ctx->pending_flush_mask |= dpu_hw_ctl_get_bitmask_mixer(ctx, LM_0 + i); > } > > DPU_REG_WRITE(c, CTL_FETCH_PIPE_ACTIVE, 0); > + > + ctx->pending_flush_mask |= CTL_FLUSH_MASK_CTL; > } > > static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 88e9cc38c13b..8b01cb660381 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -970,6 +970,8 @@ static int dpu_kms_hw_init(struct msm_kms *kms) > > dpu_kms->rm_init = true; > > + dpu_rm_clear_boot_config(&dpu_kms->rm, dpu_kms->catalog); > + > dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio, > dpu_kms->catalog); > if (IS_ERR(dpu_kms->hw_mdp)) { > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > index fd2d104f0a91..2cf47084482f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c > @@ -4,6 +4,7 @@ > */ > > #define pr_fmt(fmt) "[drm:%s] " fmt, __func__ > +#include > #include "dpu_kms.h" > #include "dpu_hw_lm.h" > #include "dpu_hw_ctl.h" > @@ -229,6 +230,41 @@ int dpu_rm_init(struct dpu_rm *rm, > return rc ? rc : -EFAULT; > } > > +void dpu_rm_clear_boot_config(struct dpu_rm *rm, struct dpu_mdss_cfg *cat) > +{ > + struct dpu_hw_intf *intf; > + struct dpu_hw_ctl *ctl; > + int i; > + > + for (i = INTF_0; i < INTF_MAX; i++) { > + if (!rm->intf_blks[i - INTF_0]) > + continue; > + > + DPU_DEBUG("disabling intf%d timing engine\n", i - INTF_0); > + > + intf = to_dpu_hw_intf(rm->intf_blks[i - INTF_0]); > + intf->ops.enable_timing(intf, 0); > + } > + > + /* > + * Wait one frame for the INTF timing engine to stop, and then wait one > + * more frame, per the documentation. > + */ > + msleep(32); > + > + for (i = CTL_0; i < CTL_MAX; i++) { > + if (!rm->ctl_blks[i - CTL_0]) > + continue; > + > + DPU_DEBUG("clearing ctl%d layer configuration\n", i - CTL_0); > + > + ctl = to_dpu_hw_ctl(rm->ctl_blks[i - CTL_0]); > + ctl->ops.clear_all_blendstages(ctl); > + ctl->ops.trigger_flush(ctl); > + ctl->ops.trigger_start(ctl); > + } > +} > + > static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top) > { > return top->num_intf > 1; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h > index 1f12c8d5b8aa..53cd649614a3 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h > @@ -88,5 +88,13 @@ void dpu_rm_release(struct dpu_global_state *global_state, > int dpu_rm_get_assigned_resources(struct dpu_rm *rm, > struct dpu_global_state *global_state, uint32_t enc_id, > enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size); > + > +/** > + * dpu_rm_clear_boot_config() - Tear down any data paths configured by boot > + * @rm: DPU Resource Manger handle > + * @cat: Pointer to hardware catalog > + */ > +void dpu_rm_clear_boot_config(struct dpu_rm *rm, struct dpu_mdss_cfg *cat); > + > #endif /* __DPU_RM_H__ */ > > -- > 2.29.2 > -- With best wishes Dmitry