* [v1 1/2] drm/msm/dp: Add basic PSR support for eDP
@ 2022-02-12 12:51 Vinod Polimera
2022-02-12 12:51 ` [v1 2/2] drm/msm/disp/dpu1: Add PSR support for eDP interface in dpu driver Vinod Polimera
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Vinod Polimera @ 2022-02-12 12:51 UTC (permalink / raw)
To: y, dri-devel, linux-arm-msm, freedreno, devicetree
Cc: Vinod Polimera, linux-kernel, robdclark, dianders, quic_sbillaka,
swboyd, quic_kalyant, quic_vproddut
Add support for basic panel self refresh (PSR) feature for eDP.
Add a new interface to set PSR state in the sink from DPU.
Program the eDP controller to issue PSR enter and exit SDP to
the sink.
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 81 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/msm/dp/dp_catalog.h | 4 ++
drivers/gpu/drm/msm/dp/dp_ctrl.c | 65 ++++++++++++++++++++++++++++-
drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 ++
drivers/gpu/drm/msm/dp/dp_display.c | 12 ++++++
drivers/gpu/drm/msm/dp/dp_drm.c | 14 ++++++-
drivers/gpu/drm/msm/dp/dp_link.c | 22 ++++++++++
drivers/gpu/drm/msm/dp/dp_panel.c | 21 ++++++++++
drivers/gpu/drm/msm/dp/dp_panel.h | 6 +++
drivers/gpu/drm/msm/dp/dp_reg.h | 19 +++++++++
drivers/gpu/drm/msm/msm_drv.h | 2 +
11 files changed, 247 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
index 6ae9b29..d20cabb 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.c
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
@@ -45,6 +45,14 @@
#define DP_INTERRUPT_STATUS2_MASK \
(DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
+#define DP_INTERRUPT_STATUS4 \
+ (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \
+ PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT)
+
+#define DP_INTERRUPT_MASK4 \
+ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \
+ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK)
+
struct dp_catalog_private {
struct device *dev;
struct dp_io *io;
@@ -343,6 +351,20 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog)
ln_mapping);
}
+void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog,
+ bool enable)
+{
+ u32 mainlink_ctrl;
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+
+ mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
+ mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE;
+ mainlink_ctrl |= (enable & DP_MAINLINK_CTRL_ENABLE);
+
+ dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
+}
+
void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
bool enable)
{
@@ -581,6 +603,51 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
}
+static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog)
+{
+ /* trigger sdp */
+ dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x1);
+ dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0);
+}
+
+void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 psr_config;
+
+ /* enable PSR1 function */
+ psr_config = dp_read_link(catalog, REG_PSR_CONFIG);
+ psr_config |= BIT(0);
+ dp_write_link(catalog, REG_PSR_CONFIG, psr_config);
+
+ dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);
+ dp_catalog_enable_sdp(catalog);
+}
+
+void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 psr_cmd;
+
+ psr_cmd = dp_read_link(catalog, REG_PSR_CMD);
+
+ /*
+ * BIT(0) - send psr entry SDP
+ * BIT(1) - sned psr exit SDP
+ */
+ psr_cmd &= ~(BIT(0) | BIT(1));
+
+ if (enter)
+ psr_cmd |= BIT(0);
+ else
+ psr_cmd |= BIT(1);
+
+ dp_catalog_enable_sdp(catalog);
+ dp_write_link(catalog, REG_PSR_CMD, psr_cmd);
+}
+
u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
@@ -608,6 +675,20 @@ u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
return isr;
}
+int dp_catalog_ctrl_get_psr_interrupt(struct dp_catalog *dp_catalog)
+{
+ struct dp_catalog_private *catalog = container_of(dp_catalog,
+ struct dp_catalog_private, dp_catalog);
+ u32 intr, intr_ack;
+
+ intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS4);
+ intr_ack = (intr & DP_INTERRUPT_STATUS4)
+ << DP_INTERRUPT_STATUS_ACK_SHIFT;
+ dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack);
+
+ return intr;
+}
+
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
{
struct dp_catalog_private *catalog = container_of(dp_catalog,
diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
index 6965afa..9b1b199 100644
--- a/drivers/gpu/drm/msm/dp/dp_catalog.h
+++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
@@ -91,6 +91,7 @@ void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
+void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
u32 stream_rate_khz, bool fixed_nvid);
@@ -101,12 +102,15 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
u32 intr_mask, bool en);
void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog);
+void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter);
u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
u8 p_level);
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
+int dp_catalog_ctrl_get_psr_interrupt(struct dp_catalog *dp_catalog);
void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
u32 dp_tu, u32 valid_boundary,
u32 valid_boundary2);
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index c724cb0..952ab96 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -20,7 +20,8 @@
#include "dp_link.h"
#define DP_KHZ_TO_HZ 1000
-#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
+#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
+#define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */
#define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
#define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
@@ -78,6 +79,7 @@ struct dp_ctrl_private {
struct dp_catalog *catalog;
struct completion idle_comp;
+ struct completion psr_op_comp;
struct completion video_comp;
};
@@ -151,6 +153,9 @@ static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
+ if (ctrl->panel->psr_cap.version)
+ config |= DP_CONFIGURATION_CTRL_SEND_VSC;
+
dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
}
@@ -1365,6 +1370,52 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
return ret;
}
+void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl)
+{
+ struct dp_ctrl_private *ctrl;
+ u8 psr_config;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+ if (!ctrl->panel->psr_cap.version)
+ return;
+
+ dp_catalog_ctrl_config_psr(ctrl->catalog);
+
+ psr_config = DP_PSR_ENABLE;
+ drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &psr_config, 1);
+}
+
+void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter)
+{
+ struct dp_ctrl_private *ctrl;
+
+ ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+
+ if (!ctrl->panel->psr_cap.version)
+ return;
+
+ if (enter) {
+ reinit_completion(&ctrl->psr_op_comp);
+ dp_catalog_ctrl_set_psr(ctrl->catalog, true);
+
+ if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
+ PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) {
+ DRM_ERROR("PSR_ENTRY timedout\n");
+ dp_catalog_ctrl_set_psr(ctrl->catalog, false);
+ return;
+ }
+
+ dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
+
+ dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false);
+ } else {
+ dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true);
+
+ dp_catalog_ctrl_set_psr(ctrl->catalog, false);
+ }
+}
+
int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
{
struct dp_ctrl_private *ctrl;
@@ -1964,6 +2015,17 @@ void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+ if (ctrl->panel->psr_cap.version) {
+ isr = dp_catalog_ctrl_get_psr_interrupt(ctrl->catalog);
+
+ if (isr == 0x1)
+ DRM_DEBUG_DP("PSR frame update done\n");
+ else if (isr == 0x10)
+ DRM_DEBUG_DP("PSR exit done\n");
+
+ complete(&ctrl->psr_op_comp);
+ }
+
isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
@@ -2010,6 +2072,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
dev_err(dev, "failed to add DP OPP table\n");
init_completion(&ctrl->idle_comp);
+ init_completion(&ctrl->psr_op_comp);
init_completion(&ctrl->video_comp);
/* in parameters */
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index 2363a2d..f623035 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -34,4 +34,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
struct dp_power *power, struct dp_catalog *catalog,
struct dp_parser *parser);
+void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enable);
+void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl);
+
#endif /* _DP_CTRL_H_ */
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 7cc4d21..fe7ceea 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -871,6 +871,10 @@ static int dp_display_post_enable(struct msm_dp *dp_display)
/* signal the connect event late to synchronize video and display */
dp_display_handle_plugged_change(dp_display, true);
+
+ if (dp->panel->psr_cap.version)
+ dp_ctrl_config_psr(dp->ctrl);
+
return 0;
}
@@ -1037,6 +1041,14 @@ static void dp_display_config_hpd(struct dp_display_private *dp)
enable_irq(dp->irq);
}
+void msm_dp_display_set_psr(struct msm_dp *dp_display, bool enter)
+{
+ struct dp_display_private *dp;
+
+ dp = container_of(dp_display, struct dp_display_private, dp_display);
+ dp_ctrl_set_psr(dp->ctrl, enter);
+}
+
static int hpd_event_thread(void *data)
{
struct dp_display_private *dp_priv;
diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
index d4d360d..6eb53a0 100644
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -123,12 +123,24 @@ static enum drm_mode_status dp_connector_mode_valid(
return dp_display_validate_mode(dp_disp, mode->clock);
}
+static struct drm_connector_state *
+edp_drm_connector_duplicate_state(struct drm_connector *connector)
+{
+ struct drm_connector_state *state;
+
+ state = drm_atomic_helper_connector_duplicate_state(connector);
+
+ state->self_refresh_aware = true;
+
+ return state;
+}
+
static const struct drm_connector_funcs dp_connector_funcs = {
.detect = dp_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
.destroy = drm_connector_cleanup,
.reset = drm_atomic_helper_connector_reset,
- .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_duplicate_state = edp_drm_connector_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
};
diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
index d4d31e5..5503c29 100644
--- a/drivers/gpu/drm/msm/dp/dp_link.c
+++ b/drivers/gpu/drm/msm/dp/dp_link.c
@@ -924,6 +924,26 @@ static int dp_link_process_phy_test_pattern_request(
return 0;
}
+static int dp_link_psr_status(struct dp_link_private *link)
+{
+ u8 status[2];
+
+ drm_dp_dpcd_read(link->aux, DP_PSR_ERROR_STATUS, status, 2);
+
+ if (status[0] & DP_PSR_LINK_CRC_ERROR)
+ DRM_ERROR("PSR LINK CRC ERROR\n");
+ else if (status[0] & DP_PSR_RFB_STORAGE_ERROR)
+ DRM_ERROR("PSR RFB STORAGE ERROR\n");
+ else if (status[0] & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
+ DRM_ERROR("PSR VSC SDP UNCORRECTABLE ERROR\n");
+ else if (status[1] & DP_PSR_CAPS_CHANGE)
+ DRM_INFO("PSR Capability Change\n");
+ else
+ return 0;
+
+ return 1;
+}
+
static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
{
return link_status[r - DP_LANE0_1_STATUS];
@@ -1042,6 +1062,8 @@ int dp_link_process_request(struct dp_link *dp_link)
dp_link->sink_request |= DP_TEST_LINK_TRAINING;
} else if (!dp_link_process_phy_test_pattern_request(link)) {
dp_link->sink_request |= DP_TEST_LINK_PHY_TEST_PATTERN;
+ } else if (dp_link_psr_status(link)) {
+ DRM_INFO("PSR IRQ_HPD received\n");
} else {
ret = dp_link_process_link_status_update(link);
if (!ret) {
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
index 71db10c..e128d73 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.c
+++ b/drivers/gpu/drm/msm/dp/dp_panel.c
@@ -19,6 +19,26 @@ struct dp_panel_private {
bool aux_cfg_update_done;
};
+static void dp_panel_read_psr_cap(struct dp_panel_private *panel)
+{
+ ssize_t rlen;
+ struct dp_panel *dp_panel;
+
+ dp_panel = &panel->dp_panel;
+
+ /* edp sink */
+ if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
+ rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT,
+ &dp_panel->psr_cap, 2);
+ if (rlen == 2) {
+ DRM_DEBUG_DP("psr version: 0x%x, psr_cap: 0x%x\n",
+ dp_panel->psr_cap.version,
+ dp_panel->psr_cap.capabilities);
+ } else
+ DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen);
+ }
+}
+
static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
{
int rc = 0;
@@ -104,6 +124,7 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
}
}
+ dp_panel_read_psr_cap(panel);
end:
return rc;
}
diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
index 9023e5b..631657a 100644
--- a/drivers/gpu/drm/msm/dp/dp_panel.h
+++ b/drivers/gpu/drm/msm/dp/dp_panel.h
@@ -34,6 +34,11 @@ struct dp_panel_in {
struct dp_catalog *catalog;
};
+struct dp_panel_psr {
+ u8 version;
+ u8 capabilities;
+};
+
struct dp_panel {
/* dpcd raw data */
u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
@@ -46,6 +51,7 @@ struct dp_panel {
struct edid *edid;
struct drm_connector *connector;
struct dp_display_mode dp_mode;
+ struct dp_panel_psr psr_cap;
bool video_test;
u32 vic;
diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index 2686028..7a0b052 100644
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -22,6 +22,20 @@
#define REG_DP_INTR_STATUS2 (0x00000024)
#define REG_DP_INTR_STATUS3 (0x00000028)
+#define REG_DP_INTR_STATUS4 (0x0000002C)
+#define PSR_UPDATE_INT (0x00000001)
+#define PSR_CAPTURE_INT (0x00000004)
+#define PSR_EXIT_INT (0x00000010)
+#define PSR_UPDATE_ERROR_INT (0x00000040)
+#define PSR_WAKE_ERROR_INT (0x00000100)
+
+#define REG_DP_INTR_MASK4 (0x00000030)
+#define PSR_UPDATE_MASK (0x00000001)
+#define PSR_CAPTURE_MASK (0x00000002)
+#define PSR_EXIT_MASK (0x00000004)
+#define PSR_UPDATE_ERROR_MASK (0x00000008)
+#define PSR_WAKE_ERROR_MASK (0x00000010)
+
#define REG_DP_DP_HPD_CTRL (0x00000000)
#define DP_DP_HPD_CTRL_HPD_EN (0x00000001)
@@ -164,6 +178,9 @@
#define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094)
#define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098)
+#define REG_PSR_CONFIG (0x00000100)
+#define REG_PSR_CMD (0x00000110)
+
#define MMSS_DP_PSR_CRC_RG (0x00000154)
#define MMSS_DP_PSR_CRC_B (0x00000158)
@@ -184,6 +201,8 @@
#define MMSS_DP_AUDIO_STREAM_0 (0x00000240)
#define MMSS_DP_AUDIO_STREAM_1 (0x00000244)
+#define MMSS_DP_SDP_CFG3 (0x0000024c)
+
#define MMSS_DP_EXTENSION_0 (0x00000250)
#define MMSS_DP_EXTENSION_1 (0x00000254)
#define MMSS_DP_EXTENSION_2 (0x00000258)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index d7574e6..28e182b 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -400,6 +400,8 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_displa
void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
+void msm_dp_display_set_psr(struct msm_dp *dp, bool enter);
+
#else
static inline int __init msm_dp_register(void)
{
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [v1 2/2] drm/msm/disp/dpu1: Add PSR support for eDP interface in dpu driver
2022-02-12 12:51 [v1 1/2] drm/msm/dp: Add basic PSR support for eDP Vinod Polimera
@ 2022-02-12 12:51 ` Vinod Polimera
2022-02-12 13:56 ` Dmitry Baryshkov
2022-02-12 13:49 ` [v1 1/2] drm/msm/dp: Add basic PSR support for eDP Dmitry Baryshkov
2022-02-15 13:47 ` Dmitry Baryshkov
2 siblings, 1 reply; 5+ messages in thread
From: Vinod Polimera @ 2022-02-12 12:51 UTC (permalink / raw)
To: y, dri-devel, linux-arm-msm, freedreno, devicetree
Cc: Vinod Polimera, linux-kernel, robdclark, dianders, quic_sbillaka,
swboyd, quic_kalyant, quic_vproddut
Enable PSR on eDP interface using drm self-refresh librabry.
This patch uses a trigger from self-refresh library to enter/exit
into PSR, when there are no updates from framework.
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com>
---
drivers/gpu/drm/bridge/panel.c | 64 +++++++++++++++++++++-----
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 30 +++++++++---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 71 ++++++++++++++++++++++++++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
4 files changed, 142 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
index b32295a..c440546 100644
--- a/drivers/gpu/drm/bridge/panel.c
+++ b/drivers/gpu/drm/bridge/panel.c
@@ -102,31 +102,71 @@ static void panel_bridge_detach(struct drm_bridge *bridge)
drm_connector_cleanup(connector);
}
-static void panel_bridge_pre_enable(struct drm_bridge *bridge)
+static void panel_bridge_pre_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
-
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *cstate;
+ int i;
+
+ if (old_bridge_state->base.state) {
+ for_each_old_crtc_in_state(old_bridge_state->base.state, crtc, cstate, i) {
+ if (cstate->self_refresh_active && cstate->active)
+ return;
+ }
+ }
drm_panel_prepare(panel_bridge->panel);
}
-static void panel_bridge_enable(struct drm_bridge *bridge)
+static void panel_bridge_enable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
-
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *cstate;
+ int i;
+
+ if (old_bridge_state->base.state) {
+ for_each_old_crtc_in_state(old_bridge_state->base.state, crtc, cstate, i) {
+ if (cstate->self_refresh_active)
+ return;
+ }
+ }
drm_panel_enable(panel_bridge->panel);
}
-static void panel_bridge_disable(struct drm_bridge *bridge)
+static void panel_bridge_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
-
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *cstate;
+ int i;
+
+ if (old_bridge_state->base.state) {
+ for_each_new_crtc_in_state(old_bridge_state->base.state, crtc, cstate, i) {
+ if (cstate->self_refresh_active)
+ return;
+ }
+ }
drm_panel_disable(panel_bridge->panel);
}
-static void panel_bridge_post_disable(struct drm_bridge *bridge)
+static void panel_bridge_post_disable(struct drm_bridge *bridge,
+ struct drm_bridge_state *old_bridge_state)
{
struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
-
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *cstate;
+ int i;
+
+ if (old_bridge_state->base.state) {
+ for_each_new_crtc_in_state(old_bridge_state->base.state, crtc, cstate, i) {
+ if (cstate->self_refresh_active)
+ return;
+ }
+ }
drm_panel_unprepare(panel_bridge->panel);
}
@@ -141,10 +181,10 @@ static int panel_bridge_get_modes(struct drm_bridge *bridge,
static const struct drm_bridge_funcs panel_bridge_bridge_funcs = {
.attach = panel_bridge_attach,
.detach = panel_bridge_detach,
- .pre_enable = panel_bridge_pre_enable,
- .enable = panel_bridge_enable,
- .disable = panel_bridge_disable,
- .post_disable = panel_bridge_post_disable,
+ .atomic_pre_enable = panel_bridge_pre_enable,
+ .atomic_enable = panel_bridge_enable,
+ .atomic_disable = panel_bridge_disable,
+ .atomic_post_disable = panel_bridge_post_disable,
.get_modes = panel_bridge_get_modes,
.atomic_reset = drm_atomic_helper_bridge_reset,
.atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index e7c9fe1..90223b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -18,6 +18,7 @@
#include <drm/drm_probe_helper.h>
#include <drm/drm_rect.h>
#include <drm/drm_vblank.h>
+#include <drm/drm_self_refresh_helper.h>
#include "dpu_kms.h"
#include "dpu_hw_lm.h"
@@ -457,7 +458,6 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
mixer[i].mixer_op_mode,
ctl->idx - CTL_0,
mixer[i].flush_mask);
-
ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
&stage_cfg);
}
@@ -951,6 +951,14 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
+ if (old_crtc_state->self_refresh_active) {
+ drm_for_each_encoder_mask(encoder, crtc->dev,
+ old_crtc_state->encoder_mask) {
+ dpu_encoder_assign_crtc(encoder, NULL);
+ }
+ return;
+ }
+
/* Disable/save vblank irq handling */
drm_crtc_vblank_off(crtc);
@@ -962,7 +970,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
*/
if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
release_bandwidth = true;
- dpu_encoder_assign_crtc(encoder, NULL);
+ if (!crtc->state->self_refresh_active)
+ dpu_encoder_assign_crtc(encoder, NULL);
}
/* wait for frame_event_done completion */
@@ -1010,6 +1019,8 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
struct drm_encoder *encoder;
bool request_bandwidth = false;
+ struct drm_crtc_state *old_crtc_state =
+ drm_atomic_get_old_crtc_state(state, crtc);
pm_runtime_get_sync(crtc->dev->dev);
@@ -1032,8 +1043,10 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
dpu_crtc->enabled = true;
- drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
- dpu_encoder_assign_crtc(encoder, crtc);
+ if (!old_crtc_state->self_refresh_active) {
+ drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
+ dpu_encoder_assign_crtc(encoder, crtc);
+ }
/* Enable/restore vblank irq handling */
drm_crtc_vblank_on(crtc);
@@ -1069,7 +1082,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
- if (!crtc_state->enable || !crtc_state->active) {
+ if (!crtc_state->enable || !crtc_state->active || crtc_state->self_refresh_active) {
DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
crtc->base.id, crtc_state->enable,
crtc_state->active);
@@ -1497,7 +1510,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
{
struct drm_crtc *crtc = NULL;
struct dpu_crtc *dpu_crtc = NULL;
- int i;
+ int i, ret;
dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
if (!dpu_crtc)
@@ -1534,6 +1547,11 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
/* initialize event handling */
spin_lock_init(&dpu_crtc->event_lock);
+ ret = drm_self_refresh_helper_init(crtc);
+ if (ret)
+ DPU_ERROR("Failed to initialize %s with SR helpers %d\n",
+ crtc->name, ret);
+
DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
return crtc;
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1e648db..461fdd1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -217,6 +217,14 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
};
+static inline bool is_self_refresh_active(struct drm_crtc_state *state)
+{
+ if (state && state->self_refresh_active)
+ return true;
+
+ return false;
+}
+
static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
{
struct dpu_hw_dither_cfg dither_cfg = { 0 };
@@ -600,6 +608,9 @@ static int dpu_encoder_virt_atomic_check(
trace_dpu_enc_atomic_check(DRMID(drm_enc));
+ if (crtc_state->self_refresh_active)
+ return ret;
+
/* perform atomic check on the first physical encoder (master) */
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -1138,15 +1149,19 @@ void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
mutex_unlock(&dpu_enc->enc_lock);
}
-static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
+static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc,
+ struct drm_atomic_state *state)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int ret = 0;
struct msm_drm_private *priv;
struct drm_display_mode *cur_mode = NULL;
+ struct drm_crtc_state *old_crtc_state;
+ struct drm_crtc *crtc;
dpu_enc = to_dpu_encoder_virt(drm_enc);
+ crtc = dpu_enc->crtc;
mutex_lock(&dpu_enc->enc_lock);
cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
priv = drm_enc->dev->dev_private;
@@ -1170,21 +1185,59 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
_dpu_encoder_virt_enable_helper(drm_enc);
- dpu_enc->enabled = true;
+ /* Coming back from self refresh, exit PSR */
+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS &&
+ is_self_refresh_active(old_crtc_state))
+ msm_dp_display_set_psr(dpu_enc->dp, false);
+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS &&
+ !is_self_refresh_active(old_crtc_state)) {
+ ret = msm_dp_display_enable(dpu_enc->dp, drm_enc);
+ if (ret) {
+ DPU_ERROR_ENC(dpu_enc, "dp display enable failed: %d\n",
+ ret);
+ goto out;
+ }
+ }
+
+ dpu_enc->enabled = true;
out:
mutex_unlock(&dpu_enc->enc_lock);
}
-static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
+static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc,
+ struct drm_atomic_state *state)
{
struct dpu_encoder_virt *dpu_enc = NULL;
struct msm_drm_private *priv;
+ struct drm_crtc *crtc;
+ struct drm_crtc_state *old_state;
int i = 0;
dpu_enc = to_dpu_encoder_virt(drm_enc);
DPU_DEBUG_ENC(dpu_enc, "\n");
+ if (!drm_enc) {
+ DPU_ERROR("invalid encoder\n");
+ return;
+ }
+ dpu_enc = to_dpu_encoder_virt(drm_enc);
+
+ crtc = dpu_enc->crtc;
+
+ /* Enter PSR if encoder supports */
+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && is_self_refresh_active(crtc->state))
+ msm_dp_display_set_psr(dpu_enc->dp, true);
+
+ old_state = drm_atomic_get_old_crtc_state(state, crtc);
+
+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && is_self_refresh_active(old_state)) {
+ msm_dp_display_set_psr(dpu_enc->dp, false);
+ if (msm_dp_display_disable(dpu_enc->dp, drm_enc))
+ DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
+ return;
+ }
+
mutex_lock(&dpu_enc->enc_lock);
dpu_enc->enabled = false;
@@ -1194,6 +1247,9 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
/* wait for idle */
dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && !is_self_refresh_active(crtc->state))
+ if (msm_dp_display_pre_disable(dpu_enc->dp, drm_enc))
+ DPU_ERROR_ENC(dpu_enc, "dp display push idle failed\n");
dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
@@ -1204,7 +1260,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
phys->ops.disable(phys);
}
-
/* after phys waits for frame-done, should be no more frames pending */
if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
@@ -1219,6 +1274,10 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
+ if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && !is_self_refresh_active(crtc->state))
+ if (msm_dp_display_disable(dpu_enc->dp, drm_enc))
+ DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
+
mutex_unlock(&dpu_enc->enc_lock);
}
@@ -2094,8 +2153,8 @@ static void dpu_encoder_frame_done_timeout(struct timer_list *t)
static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
.mode_set = dpu_encoder_virt_mode_set,
- .disable = dpu_encoder_virt_disable,
- .enable = dpu_encoder_virt_enable,
+ .atomic_disable = dpu_encoder_virt_disable,
+ .atomic_enable = dpu_encoder_virt_enable,
.atomic_check = dpu_encoder_virt_atomic_check,
};
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 47fe11a..aed8e09 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -495,7 +495,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
return;
}
- if (!crtc->state->active) {
+ if (!crtc->state->active && !crtc->state->self_refresh_active) {
DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
return;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [v1 1/2] drm/msm/dp: Add basic PSR support for eDP
2022-02-12 12:51 [v1 1/2] drm/msm/dp: Add basic PSR support for eDP Vinod Polimera
2022-02-12 12:51 ` [v1 2/2] drm/msm/disp/dpu1: Add PSR support for eDP interface in dpu driver Vinod Polimera
@ 2022-02-12 13:49 ` Dmitry Baryshkov
2022-02-15 13:47 ` Dmitry Baryshkov
2 siblings, 0 replies; 5+ messages in thread
From: Dmitry Baryshkov @ 2022-02-12 13:49 UTC (permalink / raw)
To: Vinod Polimera
Cc: y, dri-devel, linux-arm-msm, freedreno, devicetree, linux-kernel,
robdclark, dianders, quic_sbillaka, swboyd, quic_kalyant,
quic_vproddut
On Sat, 12 Feb 2022 at 15:52, Vinod Polimera <quic_vpolimer@quicinc.com> wrote:
>
> Add support for basic panel self refresh (PSR) feature for eDP.
> Add a new interface to set PSR state in the sink from DPU.
> Program the eDP controller to issue PSR enter and exit SDP to
> the sink.
>
> Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
> ---
> drivers/gpu/drm/msm/dp/dp_catalog.c | 81 +++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/dp/dp_catalog.h | 4 ++
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 65 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 ++
> drivers/gpu/drm/msm/dp/dp_display.c | 12 ++++++
> drivers/gpu/drm/msm/dp/dp_drm.c | 14 ++++++-
> drivers/gpu/drm/msm/dp/dp_link.c | 22 ++++++++++
> drivers/gpu/drm/msm/dp/dp_panel.c | 21 ++++++++++
> drivers/gpu/drm/msm/dp/dp_panel.h | 6 +++
> drivers/gpu/drm/msm/dp/dp_reg.h | 19 +++++++++
> drivers/gpu/drm/msm/msm_drv.h | 2 +
> 11 files changed, 247 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index 6ae9b29..d20cabb 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -45,6 +45,14 @@
> #define DP_INTERRUPT_STATUS2_MASK \
> (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
>
> +#define DP_INTERRUPT_STATUS4 \
> + (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \
> + PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT)
> +
> +#define DP_INTERRUPT_MASK4 \
> + (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \
> + PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK)
> +
> struct dp_catalog_private {
> struct device *dev;
> struct dp_io *io;
> @@ -343,6 +351,20 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog)
> ln_mapping);
> }
>
> +void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog,
> + bool enable)
> +{
> + u32 mainlink_ctrl;
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> +
> + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
> + mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE;
> + mainlink_ctrl |= (enable & DP_MAINLINK_CTRL_ENABLE);
> +
> + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
> +}
> +
> void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
> bool enable)
> {
> @@ -581,6 +603,51 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
> dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
> }
>
> +static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog)
> +{
> + /* trigger sdp */
> + dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x1);
> + dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0);
> +}
> +
> +void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog)
> +{
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> + u32 psr_config;
> +
> + /* enable PSR1 function */
> + psr_config = dp_read_link(catalog, REG_PSR_CONFIG);
> + psr_config |= BIT(0);
> + dp_write_link(catalog, REG_PSR_CONFIG, psr_config);
> +
> + dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);
> + dp_catalog_enable_sdp(catalog);
> +}
> +
> +void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter)
> +{
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> + u32 psr_cmd;
> +
> + psr_cmd = dp_read_link(catalog, REG_PSR_CMD);
> +
> + /*
> + * BIT(0) - send psr entry SDP
> + * BIT(1) - sned psr exit SDP
> + */
> + psr_cmd &= ~(BIT(0) | BIT(1));
> +
> + if (enter)
> + psr_cmd |= BIT(0);
> + else
> + psr_cmd |= BIT(1);
> +
> + dp_catalog_enable_sdp(catalog);
> + dp_write_link(catalog, REG_PSR_CMD, psr_cmd);
> +}
> +
> u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog)
> {
> struct dp_catalog_private *catalog = container_of(dp_catalog,
> @@ -608,6 +675,20 @@ u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
> return isr;
> }
>
> +int dp_catalog_ctrl_get_psr_interrupt(struct dp_catalog *dp_catalog)
> +{
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> + u32 intr, intr_ack;
> +
> + intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS4);
> + intr_ack = (intr & DP_INTERRUPT_STATUS4)
> + << DP_INTERRUPT_STATUS_ACK_SHIFT;
> + dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack);
> +
> + return intr;
> +}
> +
> int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
> {
> struct dp_catalog_private *catalog = container_of(dp_catalog,
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
> index 6965afa..9b1b199 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.h
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
> @@ -91,6 +91,7 @@ void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
> void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
> void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
> void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
> +void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
> void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
> void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
> u32 stream_rate_khz, bool fixed_nvid);
> @@ -101,12 +102,15 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
> void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
> u32 intr_mask, bool en);
> void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog);
> +void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog);
> +void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter);
> u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
> u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
> void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
> int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
> u8 p_level);
> int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
> +int dp_catalog_ctrl_get_psr_interrupt(struct dp_catalog *dp_catalog);
> void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
> u32 dp_tu, u32 valid_boundary,
> u32 valid_boundary2);
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index c724cb0..952ab96 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -20,7 +20,8 @@
> #include "dp_link.h"
>
> #define DP_KHZ_TO_HZ 1000
> -#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
> +#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
Please abstain from unnecessary whitespace changes
> +#define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */
> #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
>
> #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
> @@ -78,6 +79,7 @@ struct dp_ctrl_private {
> struct dp_catalog *catalog;
>
> struct completion idle_comp;
> + struct completion psr_op_comp;
> struct completion video_comp;
> };
>
> @@ -151,6 +153,9 @@ static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
> config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
> config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
>
> + if (ctrl->panel->psr_cap.version)
> + config |= DP_CONFIGURATION_CTRL_SEND_VSC;
> +
> dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
> }
>
> @@ -1365,6 +1370,52 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
> return ret;
> }
>
> +void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl)
> +{
> + struct dp_ctrl_private *ctrl;
> + u8 psr_config;
> +
> + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
> +
> + if (!ctrl->panel->psr_cap.version)
> + return;
> +
> + dp_catalog_ctrl_config_psr(ctrl->catalog);
> +
> + psr_config = DP_PSR_ENABLE;
> + drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &psr_config, 1);
> +}
> +
> +void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter)
> +{
> + struct dp_ctrl_private *ctrl;
> +
> + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
> +
> + if (!ctrl->panel->psr_cap.version)
> + return;
> +
> + if (enter) {
> + reinit_completion(&ctrl->psr_op_comp);
> + dp_catalog_ctrl_set_psr(ctrl->catalog, true);
> +
> + if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
> + PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) {
> + DRM_ERROR("PSR_ENTRY timedout\n");
> + dp_catalog_ctrl_set_psr(ctrl->catalog, false);
> + return;
> + }
> +
> + dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
> +
> + dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false);
> + } else {
> + dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true);
> +
> + dp_catalog_ctrl_set_psr(ctrl->catalog, false);
> + }
> +}
> +
> int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
> {
> struct dp_ctrl_private *ctrl;
> @@ -1964,6 +2015,17 @@ void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
>
> ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
>
> + if (ctrl->panel->psr_cap.version) {
> + isr = dp_catalog_ctrl_get_psr_interrupt(ctrl->catalog);
> +
> + if (isr == 0x1)
> + DRM_DEBUG_DP("PSR frame update done\n");
> + else if (isr == 0x10)
> + DRM_DEBUG_DP("PSR exit done\n");
> +
> + complete(&ctrl->psr_op_comp);
> + }
> +
> isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
>
> if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
> @@ -2010,6 +2072,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
> dev_err(dev, "failed to add DP OPP table\n");
>
> init_completion(&ctrl->idle_comp);
> + init_completion(&ctrl->psr_op_comp);
> init_completion(&ctrl->video_comp);
>
> /* in parameters */
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
> index 2363a2d..f623035 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
> @@ -34,4 +34,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
> struct dp_power *power, struct dp_catalog *catalog,
> struct dp_parser *parser);
>
> +void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enable);
> +void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl);
> +
> #endif /* _DP_CTRL_H_ */
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
> index 7cc4d21..fe7ceea 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -871,6 +871,10 @@ static int dp_display_post_enable(struct msm_dp *dp_display)
>
> /* signal the connect event late to synchronize video and display */
> dp_display_handle_plugged_change(dp_display, true);
> +
> + if (dp->panel->psr_cap.version)
> + dp_ctrl_config_psr(dp->ctrl);
> +
> return 0;
> }
>
> @@ -1037,6 +1041,14 @@ static void dp_display_config_hpd(struct dp_display_private *dp)
> enable_irq(dp->irq);
> }
>
> +void msm_dp_display_set_psr(struct msm_dp *dp_display, bool enter)
> +{
> + struct dp_display_private *dp;
> +
> + dp = container_of(dp_display, struct dp_display_private, dp_display);
> + dp_ctrl_set_psr(dp->ctrl, enter);
> +}
> +
> static int hpd_event_thread(void *data)
> {
> struct dp_display_private *dp_priv;
> diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
> index d4d360d..6eb53a0 100644
> --- a/drivers/gpu/drm/msm/dp/dp_drm.c
> +++ b/drivers/gpu/drm/msm/dp/dp_drm.c
> @@ -123,12 +123,24 @@ static enum drm_mode_status dp_connector_mode_valid(
> return dp_display_validate_mode(dp_disp, mode->clock);
> }
>
> +static struct drm_connector_state *
> +edp_drm_connector_duplicate_state(struct drm_connector *connector)
> +{
> + struct drm_connector_state *state;
> +
> + state = drm_atomic_helper_connector_duplicate_state(connector);
> +
> + state->self_refresh_aware = true;
state->self_refresh_aware will be copied. No need to reset it here.
I think you'd better set it in the connector's atomic_check() (at
least that's the place where analogix_dp sets it).
In the same function you have to implement the following requirement
from the docs:
If the crtc and connector are SR aware, but the panel connected does
not support it (or is otherwise unable to enter SR), the driver should
fail atomic_check when drm_crtc_state.self_refresh_active is true.
Last, but not least, judging from the rest of the code, not all DP
connectors seem to be self-refresh-aware. Please consult
psr_cap.version before setting this boolean.
> +
> + return state;
> +}
> +
> static const struct drm_connector_funcs dp_connector_funcs = {
> .detect = dp_connector_detect,
> .fill_modes = drm_helper_probe_single_connector_modes,
> .destroy = drm_connector_cleanup,
> .reset = drm_atomic_helper_connector_reset,
> - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_duplicate_state = edp_drm_connector_duplicate_state,
> .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> };
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
> index d4d31e5..5503c29 100644
> --- a/drivers/gpu/drm/msm/dp/dp_link.c
> +++ b/drivers/gpu/drm/msm/dp/dp_link.c
> @@ -924,6 +924,26 @@ static int dp_link_process_phy_test_pattern_request(
> return 0;
> }
>
> +static int dp_link_psr_status(struct dp_link_private *link)
> +{
> + u8 status[2];
> +
> + drm_dp_dpcd_read(link->aux, DP_PSR_ERROR_STATUS, status, 2);
> +
> + if (status[0] & DP_PSR_LINK_CRC_ERROR)
> + DRM_ERROR("PSR LINK CRC ERROR\n");
> + else if (status[0] & DP_PSR_RFB_STORAGE_ERROR)
> + DRM_ERROR("PSR RFB STORAGE ERROR\n");
> + else if (status[0] & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
> + DRM_ERROR("PSR VSC SDP UNCORRECTABLE ERROR\n");
> + else if (status[1] & DP_PSR_CAPS_CHANGE)
> + DRM_INFO("PSR Capability Change\n");
> + else
> + return 0;
> +
> + return 1;
> +}
> +
> static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
> {
> return link_status[r - DP_LANE0_1_STATUS];
> @@ -1042,6 +1062,8 @@ int dp_link_process_request(struct dp_link *dp_link)
> dp_link->sink_request |= DP_TEST_LINK_TRAINING;
> } else if (!dp_link_process_phy_test_pattern_request(link)) {
> dp_link->sink_request |= DP_TEST_LINK_PHY_TEST_PATTERN;
> + } else if (dp_link_psr_status(link)) {
> + DRM_INFO("PSR IRQ_HPD received\n");
> } else {
> ret = dp_link_process_link_status_update(link);
> if (!ret) {
> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
> index 71db10c..e128d73 100644
> --- a/drivers/gpu/drm/msm/dp/dp_panel.c
> +++ b/drivers/gpu/drm/msm/dp/dp_panel.c
> @@ -19,6 +19,26 @@ struct dp_panel_private {
> bool aux_cfg_update_done;
> };
>
> +static void dp_panel_read_psr_cap(struct dp_panel_private *panel)
> +{
> + ssize_t rlen;
> + struct dp_panel *dp_panel;
> +
> + dp_panel = &panel->dp_panel;
> +
> + /* edp sink */
> + if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
> + rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT,
> + &dp_panel->psr_cap, 2);
> + if (rlen == 2) {
> + DRM_DEBUG_DP("psr version: 0x%x, psr_cap: 0x%x\n",
> + dp_panel->psr_cap.version,
> + dp_panel->psr_cap.capabilities);
> + } else
> + DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen);
> + }
> +}
> +
> static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
> {
> int rc = 0;
> @@ -104,6 +124,7 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
> }
> }
>
> + dp_panel_read_psr_cap(panel);
> end:
> return rc;
> }
> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
> index 9023e5b..631657a 100644
> --- a/drivers/gpu/drm/msm/dp/dp_panel.h
> +++ b/drivers/gpu/drm/msm/dp/dp_panel.h
> @@ -34,6 +34,11 @@ struct dp_panel_in {
> struct dp_catalog *catalog;
> };
>
> +struct dp_panel_psr {
> + u8 version;
> + u8 capabilities;
> +};
> +
> struct dp_panel {
> /* dpcd raw data */
> u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
> @@ -46,6 +51,7 @@ struct dp_panel {
> struct edid *edid;
> struct drm_connector *connector;
> struct dp_display_mode dp_mode;
> + struct dp_panel_psr psr_cap;
> bool video_test;
>
> u32 vic;
> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
> index 2686028..7a0b052 100644
> --- a/drivers/gpu/drm/msm/dp/dp_reg.h
> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
> @@ -22,6 +22,20 @@
> #define REG_DP_INTR_STATUS2 (0x00000024)
> #define REG_DP_INTR_STATUS3 (0x00000028)
>
> +#define REG_DP_INTR_STATUS4 (0x0000002C)
> +#define PSR_UPDATE_INT (0x00000001)
> +#define PSR_CAPTURE_INT (0x00000004)
> +#define PSR_EXIT_INT (0x00000010)
> +#define PSR_UPDATE_ERROR_INT (0x00000040)
> +#define PSR_WAKE_ERROR_INT (0x00000100)
> +
> +#define REG_DP_INTR_MASK4 (0x00000030)
> +#define PSR_UPDATE_MASK (0x00000001)
> +#define PSR_CAPTURE_MASK (0x00000002)
> +#define PSR_EXIT_MASK (0x00000004)
> +#define PSR_UPDATE_ERROR_MASK (0x00000008)
> +#define PSR_WAKE_ERROR_MASK (0x00000010)
> +
> #define REG_DP_DP_HPD_CTRL (0x00000000)
> #define DP_DP_HPD_CTRL_HPD_EN (0x00000001)
>
> @@ -164,6 +178,9 @@
> #define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094)
> #define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098)
>
> +#define REG_PSR_CONFIG (0x00000100)
> +#define REG_PSR_CMD (0x00000110)
> +
> #define MMSS_DP_PSR_CRC_RG (0x00000154)
> #define MMSS_DP_PSR_CRC_B (0x00000158)
>
> @@ -184,6 +201,8 @@
> #define MMSS_DP_AUDIO_STREAM_0 (0x00000240)
> #define MMSS_DP_AUDIO_STREAM_1 (0x00000244)
>
> +#define MMSS_DP_SDP_CFG3 (0x0000024c)
> +
> #define MMSS_DP_EXTENSION_0 (0x00000250)
> #define MMSS_DP_EXTENSION_1 (0x00000254)
> #define MMSS_DP_EXTENSION_2 (0x00000258)
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d7574e6..28e182b 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -400,6 +400,8 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_displa
>
> void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
>
> +void msm_dp_display_set_psr(struct msm_dp *dp, bool enter);
Please provide a stub in the #else branch below. Otherwise compilation
would break if CONFIG_DRM_MSM_DP is disabled.
> +
> #else
> static inline int __init msm_dp_register(void)
> {
> --
> 2.7.4
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [v1 2/2] drm/msm/disp/dpu1: Add PSR support for eDP interface in dpu driver
2022-02-12 12:51 ` [v1 2/2] drm/msm/disp/dpu1: Add PSR support for eDP interface in dpu driver Vinod Polimera
@ 2022-02-12 13:56 ` Dmitry Baryshkov
0 siblings, 0 replies; 5+ messages in thread
From: Dmitry Baryshkov @ 2022-02-12 13:56 UTC (permalink / raw)
To: Vinod Polimera
Cc: y, dri-devel, linux-arm-msm, freedreno, devicetree, linux-kernel,
robdclark, dianders, quic_sbillaka, swboyd, quic_kalyant,
quic_vproddut
On Sat, 12 Feb 2022 at 15:52, Vinod Polimera <quic_vpolimer@quicinc.com> wrote:
>
> Enable PSR on eDP interface using drm self-refresh librabry.
> This patch uses a trigger from self-refresh library to enter/exit
> into PSR, when there are no updates from framework.
>
> Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
> Signed-off-by: Kalyan Thota <quic_kalyant@quicinc.com>
The S-O-B of the sender should come last. Please change the order of
the S-O-B tags.
> ---
> drivers/gpu/drm/bridge/panel.c | 64 +++++++++++++++++++++-----
This chunk should come in a separate patch. Please do not mix drm/msm
patches with the generic code.
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 30 +++++++++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 71 ++++++++++++++++++++++++++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
> 4 files changed, 142 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
> index b32295a..c440546 100644
> --- a/drivers/gpu/drm/bridge/panel.c
> +++ b/drivers/gpu/drm/bridge/panel.c
> @@ -102,31 +102,71 @@ static void panel_bridge_detach(struct drm_bridge *bridge)
> drm_connector_cleanup(connector);
> }
>
> -static void panel_bridge_pre_enable(struct drm_bridge *bridge)
> +static void panel_bridge_pre_enable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> {
> struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
> -
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *cstate;
> + int i;
> +
> + if (old_bridge_state->base.state) {
> + for_each_old_crtc_in_state(old_bridge_state->base.state, crtc, cstate, i) {
> + if (cstate->self_refresh_active && cstate->active)
> + return;
> + }
Ugh. No. You will skip panel actions if _any_ of the crtc's has PSR
enabled. There might be other CRTCs in play.
Please see analogix_dp_core.c for a proper way to handle this.
Consider moving common code (e.g. getting the crtc used by the
encoder) pieces to the generic drm code.
> + }
> drm_panel_prepare(panel_bridge->panel);
> }
>
> -static void panel_bridge_enable(struct drm_bridge *bridge)
> +static void panel_bridge_enable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> {
> struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
> -
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *cstate;
> + int i;
> +
> + if (old_bridge_state->base.state) {
> + for_each_old_crtc_in_state(old_bridge_state->base.state, crtc, cstate, i) {
> + if (cstate->self_refresh_active)
> + return;
> + }
> + }
> drm_panel_enable(panel_bridge->panel);
> }
>
> -static void panel_bridge_disable(struct drm_bridge *bridge)
> +static void panel_bridge_disable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> {
> struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
> -
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *cstate;
> + int i;
> +
> + if (old_bridge_state->base.state) {
> + for_each_new_crtc_in_state(old_bridge_state->base.state, crtc, cstate, i) {
> + if (cstate->self_refresh_active)
> + return;
> + }
> + }
> drm_panel_disable(panel_bridge->panel);
> }
>
> -static void panel_bridge_post_disable(struct drm_bridge *bridge)
> +static void panel_bridge_post_disable(struct drm_bridge *bridge,
> + struct drm_bridge_state *old_bridge_state)
> {
> struct panel_bridge *panel_bridge = drm_bridge_to_panel_bridge(bridge);
> -
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *cstate;
> + int i;
> +
> + if (old_bridge_state->base.state) {
> + for_each_new_crtc_in_state(old_bridge_state->base.state, crtc, cstate, i) {
> + if (cstate->self_refresh_active)
> + return;
> + }
> + }
> drm_panel_unprepare(panel_bridge->panel);
> }
>
> @@ -141,10 +181,10 @@ static int panel_bridge_get_modes(struct drm_bridge *bridge,
> static const struct drm_bridge_funcs panel_bridge_bridge_funcs = {
> .attach = panel_bridge_attach,
> .detach = panel_bridge_detach,
> - .pre_enable = panel_bridge_pre_enable,
> - .enable = panel_bridge_enable,
> - .disable = panel_bridge_disable,
> - .post_disable = panel_bridge_post_disable,
> + .atomic_pre_enable = panel_bridge_pre_enable,
> + .atomic_enable = panel_bridge_enable,
> + .atomic_disable = panel_bridge_disable,
> + .atomic_post_disable = panel_bridge_post_disable,
> .get_modes = panel_bridge_get_modes,
> .atomic_reset = drm_atomic_helper_bridge_reset,
> .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index e7c9fe1..90223b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -18,6 +18,7 @@
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_rect.h>
> #include <drm/drm_vblank.h>
> +#include <drm/drm_self_refresh_helper.h>
>
> #include "dpu_kms.h"
> #include "dpu_hw_lm.h"
> @@ -457,7 +458,6 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
> mixer[i].mixer_op_mode,
> ctl->idx - CTL_0,
> mixer[i].flush_mask);
> -
Unnecessary
> ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
> &stage_cfg);
> }
> @@ -951,6 +951,14 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
>
> DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
>
> + if (old_crtc_state->self_refresh_active) {
> + drm_for_each_encoder_mask(encoder, crtc->dev,
> + old_crtc_state->encoder_mask) {
> + dpu_encoder_assign_crtc(encoder, NULL);
> + }
> + return;
> + }
> +
> /* Disable/save vblank irq handling */
> drm_crtc_vblank_off(crtc);
>
> @@ -962,7 +970,8 @@ static void dpu_crtc_disable(struct drm_crtc *crtc,
> */
> if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
> release_bandwidth = true;
> - dpu_encoder_assign_crtc(encoder, NULL);
> + if (!crtc->state->self_refresh_active)
> + dpu_encoder_assign_crtc(encoder, NULL);
This deserves some comments in the code
> }
>
> /* wait for frame_event_done completion */
> @@ -1010,6 +1019,8 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
> struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
> struct drm_encoder *encoder;
> bool request_bandwidth = false;
> + struct drm_crtc_state *old_crtc_state =
> + drm_atomic_get_old_crtc_state(state, crtc);
>
> pm_runtime_get_sync(crtc->dev->dev);
>
> @@ -1032,8 +1043,10 @@ static void dpu_crtc_enable(struct drm_crtc *crtc,
> trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
> dpu_crtc->enabled = true;
>
> - drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
> - dpu_encoder_assign_crtc(encoder, crtc);
> + if (!old_crtc_state->self_refresh_active) {
> + drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
> + dpu_encoder_assign_crtc(encoder, crtc);
> + }
This deserves some comments in the code
>
> /* Enable/restore vblank irq handling */
> drm_crtc_vblank_on(crtc);
> @@ -1069,7 +1082,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
>
> pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
>
> - if (!crtc_state->enable || !crtc_state->active) {
> + if (!crtc_state->enable || !crtc_state->active || crtc_state->self_refresh_active) {
This does not seem correct to me. According to the docs: "When in self
refresh mode, the crtc_state->active value will be false, since the
CRTC is off."
> DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
> crtc->base.id, crtc_state->enable,
> crtc_state->active);
> @@ -1497,7 +1510,7 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
> {
> struct drm_crtc *crtc = NULL;
> struct dpu_crtc *dpu_crtc = NULL;
> - int i;
> + int i, ret;
>
> dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
> if (!dpu_crtc)
> @@ -1534,6 +1547,11 @@ struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
> /* initialize event handling */
> spin_lock_init(&dpu_crtc->event_lock);
>
> + ret = drm_self_refresh_helper_init(crtc);
> + if (ret)
> + DPU_ERROR("Failed to initialize %s with SR helpers %d\n",
> + crtc->name, ret);
> +
> DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
> return crtc;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db..461fdd1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -217,6 +217,14 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = {
> 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10
> };
>
> +static inline bool is_self_refresh_active(struct drm_crtc_state *state)
> +{
> + if (state && state->self_refresh_active)
> + return true;
> +
> + return false;
> +}
> +
> static void _dpu_encoder_setup_dither(struct dpu_hw_pingpong *hw_pp, unsigned bpc)
> {
> struct dpu_hw_dither_cfg dither_cfg = { 0 };
> @@ -600,6 +608,9 @@ static int dpu_encoder_virt_atomic_check(
>
> trace_dpu_enc_atomic_check(DRMID(drm_enc));
>
> + if (crtc_state->self_refresh_active)
> + return ret;
> +
Why?
> /* perform atomic check on the first physical encoder (master) */
> for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> @@ -1138,15 +1149,19 @@ void dpu_encoder_virt_runtime_resume(struct drm_encoder *drm_enc)
> mutex_unlock(&dpu_enc->enc_lock);
> }
>
> -static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
> +static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc,
> + struct drm_atomic_state *state)
> {
> struct dpu_encoder_virt *dpu_enc = NULL;
> int ret = 0;
> struct msm_drm_private *priv;
> struct drm_display_mode *cur_mode = NULL;
> + struct drm_crtc_state *old_crtc_state;
> + struct drm_crtc *crtc;
>
> dpu_enc = to_dpu_encoder_virt(drm_enc);
>
> + crtc = dpu_enc->crtc;
> mutex_lock(&dpu_enc->enc_lock);
> cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
> priv = drm_enc->dev->dev_private;
> @@ -1170,21 +1185,59 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
>
> _dpu_encoder_virt_enable_helper(drm_enc);
>
> - dpu_enc->enabled = true;
> + /* Coming back from self refresh, exit PSR */
> + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS &&
> + is_self_refresh_active(old_crtc_state))
> + msm_dp_display_set_psr(dpu_enc->dp, false);
>
> + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS &&
> + !is_self_refresh_active(old_crtc_state)) {
> + ret = msm_dp_display_enable(dpu_enc->dp, drm_enc);
You shouldn't call msm_dp_display_*() directly.
I might be wrong, but I think that these function calls should be
moved into dp_bridge code instead of taking place here.
> + if (ret) {
> + DPU_ERROR_ENC(dpu_enc, "dp display enable failed: %d\n",
> + ret);
> + goto out;
> + }
> + }
> +
> + dpu_enc->enabled = true;
> out:
> mutex_unlock(&dpu_enc->enc_lock);
> }
>
> -static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
> +static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc,
> + struct drm_atomic_state *state)
> {
> struct dpu_encoder_virt *dpu_enc = NULL;
> struct msm_drm_private *priv;
> + struct drm_crtc *crtc;
> + struct drm_crtc_state *old_state;
> int i = 0;
>
> dpu_enc = to_dpu_encoder_virt(drm_enc);
> DPU_DEBUG_ENC(dpu_enc, "\n");
>
> + if (!drm_enc) {
> + DPU_ERROR("invalid encoder\n");
> + return;
> + }
> + dpu_enc = to_dpu_encoder_virt(drm_enc);
> +
> + crtc = dpu_enc->crtc;
> +
> + /* Enter PSR if encoder supports */
> + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && is_self_refresh_active(crtc->state))
> + msm_dp_display_set_psr(dpu_enc->dp, true);
> +
> + old_state = drm_atomic_get_old_crtc_state(state, crtc);
> +
> + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && is_self_refresh_active(old_state)) {
> + msm_dp_display_set_psr(dpu_enc->dp, false);
> + if (msm_dp_display_disable(dpu_enc->dp, drm_enc))
> + DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
> + return;
> + }
> +
> mutex_lock(&dpu_enc->enc_lock);
> dpu_enc->enabled = false;
>
> @@ -1194,6 +1247,9 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
>
> /* wait for idle */
> dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
> + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && !is_self_refresh_active(crtc->state))
> + if (msm_dp_display_pre_disable(dpu_enc->dp, drm_enc))
> + DPU_ERROR_ENC(dpu_enc, "dp display push idle failed\n");
>
> dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP);
>
> @@ -1204,7 +1260,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
> phys->ops.disable(phys);
> }
>
> -
> /* after phys waits for frame-done, should be no more frames pending */
> if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {
> DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
> @@ -1219,6 +1274,10 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
>
> DPU_DEBUG_ENC(dpu_enc, "encoder disabled\n");
>
> + if (drm_enc->encoder_type == DRM_MODE_ENCODER_TMDS && !is_self_refresh_active(crtc->state))
> + if (msm_dp_display_disable(dpu_enc->dp, drm_enc))
> + DPU_ERROR_ENC(dpu_enc, "dp display disable failed\n");
> +
> mutex_unlock(&dpu_enc->enc_lock);
> }
>
> @@ -2094,8 +2153,8 @@ static void dpu_encoder_frame_done_timeout(struct timer_list *t)
>
> static const struct drm_encoder_helper_funcs dpu_encoder_helper_funcs = {
> .mode_set = dpu_encoder_virt_mode_set,
> - .disable = dpu_encoder_virt_disable,
> - .enable = dpu_encoder_virt_enable,
> + .atomic_disable = dpu_encoder_virt_disable,
> + .atomic_enable = dpu_encoder_virt_enable,
Please split this into a separate commit. First you convert
dpu_encoder to use atomic_enable/atomic_disable, then you add PSR
support.
> .atomic_check = dpu_encoder_virt_atomic_check,
> };
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 47fe11a..aed8e09 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -495,7 +495,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
> return;
> }
>
> - if (!crtc->state->active) {
> + if (!crtc->state->active && !crtc->state->self_refresh_active) {
drm_atomic_crtc_effectively_active() ?
> DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
> return;
> }
> --
> 2.7.4
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [v1 1/2] drm/msm/dp: Add basic PSR support for eDP
2022-02-12 12:51 [v1 1/2] drm/msm/dp: Add basic PSR support for eDP Vinod Polimera
2022-02-12 12:51 ` [v1 2/2] drm/msm/disp/dpu1: Add PSR support for eDP interface in dpu driver Vinod Polimera
2022-02-12 13:49 ` [v1 1/2] drm/msm/dp: Add basic PSR support for eDP Dmitry Baryshkov
@ 2022-02-15 13:47 ` Dmitry Baryshkov
2 siblings, 0 replies; 5+ messages in thread
From: Dmitry Baryshkov @ 2022-02-15 13:47 UTC (permalink / raw)
To: Vinod Polimera, y, dri-devel, linux-arm-msm, freedreno, devicetree
Cc: linux-kernel, robdclark, dianders, quic_sbillaka, swboyd,
quic_kalyant, quic_vproddut
On 12/02/2022 15:51, Vinod Polimera wrote:
> Add support for basic panel self refresh (PSR) feature for eDP.
> Add a new interface to set PSR state in the sink from DPU.
> Program the eDP controller to issue PSR enter and exit SDP to
> the sink.
>
> Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
Just noticed, thanks to the patchwork. Please do not send patches in
reply to other patchsets/threads. This will confuse both reviwers and
the patchwork.
> ---
> drivers/gpu/drm/msm/dp/dp_catalog.c | 81 +++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/dp/dp_catalog.h | 4 ++
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 65 ++++++++++++++++++++++++++++-
> drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 ++
> drivers/gpu/drm/msm/dp/dp_display.c | 12 ++++++
> drivers/gpu/drm/msm/dp/dp_drm.c | 14 ++++++-
> drivers/gpu/drm/msm/dp/dp_link.c | 22 ++++++++++
> drivers/gpu/drm/msm/dp/dp_panel.c | 21 ++++++++++
> drivers/gpu/drm/msm/dp/dp_panel.h | 6 +++
> drivers/gpu/drm/msm/dp/dp_reg.h | 19 +++++++++
> drivers/gpu/drm/msm/msm_drv.h | 2 +
> 11 files changed, 247 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c
> index 6ae9b29..d20cabb 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> @@ -45,6 +45,14 @@
> #define DP_INTERRUPT_STATUS2_MASK \
> (DP_INTERRUPT_STATUS2 << DP_INTERRUPT_STATUS_MASK_SHIFT)
>
> +#define DP_INTERRUPT_STATUS4 \
> + (PSR_UPDATE_INT | PSR_CAPTURE_INT | PSR_EXIT_INT | \
> + PSR_UPDATE_ERROR_INT | PSR_WAKE_ERROR_INT)
> +
> +#define DP_INTERRUPT_MASK4 \
> + (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \
> + PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK)
> +
> struct dp_catalog_private {
> struct device *dev;
> struct dp_io *io;
> @@ -343,6 +351,20 @@ void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog)
> ln_mapping);
> }
>
> +void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog,
> + bool enable)
> +{
> + u32 mainlink_ctrl;
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> +
> + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
> + mainlink_ctrl &= ~DP_MAINLINK_CTRL_ENABLE;
> + mainlink_ctrl |= (enable & DP_MAINLINK_CTRL_ENABLE);
> +
> + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
> +}
> +
> void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog,
> bool enable)
> {
> @@ -581,6 +603,51 @@ void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog)
> dp_write_aux(catalog, REG_DP_DP_HPD_CTRL, DP_DP_HPD_CTRL_HPD_EN);
> }
>
> +static void dp_catalog_enable_sdp(struct dp_catalog_private *catalog)
> +{
> + /* trigger sdp */
> + dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x1);
> + dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x0);
> +}
> +
> +void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog)
> +{
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> + u32 psr_config;
> +
> + /* enable PSR1 function */
> + psr_config = dp_read_link(catalog, REG_PSR_CONFIG);
> + psr_config |= BIT(0);
> + dp_write_link(catalog, REG_PSR_CONFIG, psr_config);
> +
> + dp_write_ahb(catalog, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4);
> + dp_catalog_enable_sdp(catalog);
> +}
> +
> +void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter)
> +{
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> + u32 psr_cmd;
> +
> + psr_cmd = dp_read_link(catalog, REG_PSR_CMD);
> +
> + /*
> + * BIT(0) - send psr entry SDP
> + * BIT(1) - sned psr exit SDP
> + */
> + psr_cmd &= ~(BIT(0) | BIT(1));
> +
> + if (enter)
> + psr_cmd |= BIT(0);
> + else
> + psr_cmd |= BIT(1);
> +
> + dp_catalog_enable_sdp(catalog);
> + dp_write_link(catalog, REG_PSR_CMD, psr_cmd);
> +}
> +
> u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog)
> {
> struct dp_catalog_private *catalog = container_of(dp_catalog,
> @@ -608,6 +675,20 @@ u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog)
> return isr;
> }
>
> +int dp_catalog_ctrl_get_psr_interrupt(struct dp_catalog *dp_catalog)
> +{
> + struct dp_catalog_private *catalog = container_of(dp_catalog,
> + struct dp_catalog_private, dp_catalog);
> + u32 intr, intr_ack;
> +
> + intr = dp_read_ahb(catalog, REG_DP_INTR_STATUS4);
> + intr_ack = (intr & DP_INTERRUPT_STATUS4)
> + << DP_INTERRUPT_STATUS_ACK_SHIFT;
> + dp_write_ahb(catalog, REG_DP_INTR_STATUS4, intr_ack);
> +
> + return intr;
> +}
> +
> int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog)
> {
> struct dp_catalog_private *catalog = container_of(dp_catalog,
> diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h
> index 6965afa..9b1b199 100644
> --- a/drivers/gpu/drm/msm/dp/dp_catalog.h
> +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
> @@ -91,6 +91,7 @@ void dp_catalog_ctrl_state_ctrl(struct dp_catalog *dp_catalog, u32 state);
> void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config);
> void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
> void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable);
> +void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable);
> void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb);
> void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate,
> u32 stream_rate_khz, bool fixed_nvid);
> @@ -101,12 +102,15 @@ void dp_catalog_ctrl_enable_irq(struct dp_catalog *dp_catalog, bool enable);
> void dp_catalog_hpd_config_intr(struct dp_catalog *dp_catalog,
> u32 intr_mask, bool en);
> void dp_catalog_ctrl_hpd_config(struct dp_catalog *dp_catalog);
> +void dp_catalog_ctrl_config_psr(struct dp_catalog *dp_catalog);
> +void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter);
> u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
> u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
> void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
> int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
> u8 p_level);
> int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
> +int dp_catalog_ctrl_get_psr_interrupt(struct dp_catalog *dp_catalog);
> void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
> u32 dp_tu, u32 valid_boundary,
> u32 valid_boundary2);
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> index c724cb0..952ab96 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> @@ -20,7 +20,8 @@
> #include "dp_link.h"
>
> #define DP_KHZ_TO_HZ 1000
> -#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
> +#define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */
> +#define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */
> #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2)
>
> #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0)
> @@ -78,6 +79,7 @@ struct dp_ctrl_private {
> struct dp_catalog *catalog;
>
> struct completion idle_comp;
> + struct completion psr_op_comp;
> struct completion video_comp;
> };
>
> @@ -151,6 +153,9 @@ static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl)
> config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN;
> config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK;
>
> + if (ctrl->panel->psr_cap.version)
> + config |= DP_CONFIGURATION_CTRL_SEND_VSC;
> +
> dp_catalog_ctrl_config_ctrl(ctrl->catalog, config);
> }
>
> @@ -1365,6 +1370,52 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
> return ret;
> }
>
> +void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl)
> +{
> + struct dp_ctrl_private *ctrl;
> + u8 psr_config;
> +
> + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
> +
> + if (!ctrl->panel->psr_cap.version)
> + return;
> +
> + dp_catalog_ctrl_config_psr(ctrl->catalog);
> +
> + psr_config = DP_PSR_ENABLE;
> + drm_dp_dpcd_write(ctrl->aux, DP_PSR_EN_CFG, &psr_config, 1);
> +}
> +
> +void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter)
> +{
> + struct dp_ctrl_private *ctrl;
> +
> + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
> +
> + if (!ctrl->panel->psr_cap.version)
> + return;
> +
> + if (enter) {
> + reinit_completion(&ctrl->psr_op_comp);
> + dp_catalog_ctrl_set_psr(ctrl->catalog, true);
> +
> + if (!wait_for_completion_timeout(&ctrl->psr_op_comp,
> + PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) {
> + DRM_ERROR("PSR_ENTRY timedout\n");
> + dp_catalog_ctrl_set_psr(ctrl->catalog, false);
> + return;
> + }
> +
> + dp_catalog_ctrl_state_ctrl(ctrl->catalog, 0);
> +
> + dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, false);
> + } else {
> + dp_catalog_ctrl_psr_mainlink_enable(ctrl->catalog, true);
> +
> + dp_catalog_ctrl_set_psr(ctrl->catalog, false);
> + }
> +}
> +
> int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip, bool reset)
> {
> struct dp_ctrl_private *ctrl;
> @@ -1964,6 +2015,17 @@ void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
>
> ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
>
> + if (ctrl->panel->psr_cap.version) {
> + isr = dp_catalog_ctrl_get_psr_interrupt(ctrl->catalog);
> +
> + if (isr == 0x1)
> + DRM_DEBUG_DP("PSR frame update done\n");
> + else if (isr == 0x10)
> + DRM_DEBUG_DP("PSR exit done\n");
> +
> + complete(&ctrl->psr_op_comp);
> + }
> +
> isr = dp_catalog_ctrl_get_interrupt(ctrl->catalog);
>
> if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) {
> @@ -2010,6 +2072,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
> dev_err(dev, "failed to add DP OPP table\n");
>
> init_completion(&ctrl->idle_comp);
> + init_completion(&ctrl->psr_op_comp);
> init_completion(&ctrl->video_comp);
>
> /* in parameters */
> diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
> index 2363a2d..f623035 100644
> --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
> +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
> @@ -34,4 +34,7 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
> struct dp_power *power, struct dp_catalog *catalog,
> struct dp_parser *parser);
>
> +void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enable);
> +void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl);
> +
> #endif /* _DP_CTRL_H_ */
> diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
> index 7cc4d21..fe7ceea 100644
> --- a/drivers/gpu/drm/msm/dp/dp_display.c
> +++ b/drivers/gpu/drm/msm/dp/dp_display.c
> @@ -871,6 +871,10 @@ static int dp_display_post_enable(struct msm_dp *dp_display)
>
> /* signal the connect event late to synchronize video and display */
> dp_display_handle_plugged_change(dp_display, true);
> +
> + if (dp->panel->psr_cap.version)
> + dp_ctrl_config_psr(dp->ctrl);
> +
> return 0;
> }
>
> @@ -1037,6 +1041,14 @@ static void dp_display_config_hpd(struct dp_display_private *dp)
> enable_irq(dp->irq);
> }
>
> +void msm_dp_display_set_psr(struct msm_dp *dp_display, bool enter)
> +{
> + struct dp_display_private *dp;
> +
> + dp = container_of(dp_display, struct dp_display_private, dp_display);
> + dp_ctrl_set_psr(dp->ctrl, enter);
> +}
> +
> static int hpd_event_thread(void *data)
> {
> struct dp_display_private *dp_priv;
> diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c
> index d4d360d..6eb53a0 100644
> --- a/drivers/gpu/drm/msm/dp/dp_drm.c
> +++ b/drivers/gpu/drm/msm/dp/dp_drm.c
> @@ -123,12 +123,24 @@ static enum drm_mode_status dp_connector_mode_valid(
> return dp_display_validate_mode(dp_disp, mode->clock);
> }
>
> +static struct drm_connector_state *
> +edp_drm_connector_duplicate_state(struct drm_connector *connector)
> +{
> + struct drm_connector_state *state;
> +
> + state = drm_atomic_helper_connector_duplicate_state(connector);
> +
> + state->self_refresh_aware = true;
> +
> + return state;
> +}
> +
> static const struct drm_connector_funcs dp_connector_funcs = {
> .detect = dp_connector_detect,
> .fill_modes = drm_helper_probe_single_connector_modes,
> .destroy = drm_connector_cleanup,
> .reset = drm_atomic_helper_connector_reset,
> - .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_duplicate_state = edp_drm_connector_duplicate_state,
> .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> };
>
> diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_link.c
> index d4d31e5..5503c29 100644
> --- a/drivers/gpu/drm/msm/dp/dp_link.c
> +++ b/drivers/gpu/drm/msm/dp/dp_link.c
> @@ -924,6 +924,26 @@ static int dp_link_process_phy_test_pattern_request(
> return 0;
> }
>
> +static int dp_link_psr_status(struct dp_link_private *link)
> +{
> + u8 status[2];
> +
> + drm_dp_dpcd_read(link->aux, DP_PSR_ERROR_STATUS, status, 2);
> +
> + if (status[0] & DP_PSR_LINK_CRC_ERROR)
> + DRM_ERROR("PSR LINK CRC ERROR\n");
> + else if (status[0] & DP_PSR_RFB_STORAGE_ERROR)
> + DRM_ERROR("PSR RFB STORAGE ERROR\n");
> + else if (status[0] & DP_PSR_VSC_SDP_UNCORRECTABLE_ERROR)
> + DRM_ERROR("PSR VSC SDP UNCORRECTABLE ERROR\n");
> + else if (status[1] & DP_PSR_CAPS_CHANGE)
> + DRM_INFO("PSR Capability Change\n");
> + else
> + return 0;
> +
> + return 1;
> +}
> +
> static u8 get_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
> {
> return link_status[r - DP_LANE0_1_STATUS];
> @@ -1042,6 +1062,8 @@ int dp_link_process_request(struct dp_link *dp_link)
> dp_link->sink_request |= DP_TEST_LINK_TRAINING;
> } else if (!dp_link_process_phy_test_pattern_request(link)) {
> dp_link->sink_request |= DP_TEST_LINK_PHY_TEST_PATTERN;
> + } else if (dp_link_psr_status(link)) {
> + DRM_INFO("PSR IRQ_HPD received\n");
> } else {
> ret = dp_link_process_link_status_update(link);
> if (!ret) {
> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c
> index 71db10c..e128d73 100644
> --- a/drivers/gpu/drm/msm/dp/dp_panel.c
> +++ b/drivers/gpu/drm/msm/dp/dp_panel.c
> @@ -19,6 +19,26 @@ struct dp_panel_private {
> bool aux_cfg_update_done;
> };
>
> +static void dp_panel_read_psr_cap(struct dp_panel_private *panel)
> +{
> + ssize_t rlen;
> + struct dp_panel *dp_panel;
> +
> + dp_panel = &panel->dp_panel;
> +
> + /* edp sink */
> + if (dp_panel->dpcd[DP_EDP_CONFIGURATION_CAP]) {
> + rlen = drm_dp_dpcd_read(panel->aux, DP_PSR_SUPPORT,
> + &dp_panel->psr_cap, 2);
> + if (rlen == 2) {
> + DRM_DEBUG_DP("psr version: 0x%x, psr_cap: 0x%x\n",
> + dp_panel->psr_cap.version,
> + dp_panel->psr_cap.capabilities);
> + } else
> + DRM_ERROR("failed to read psr info, rlen=%zd\n", rlen);
> + }
> +}
> +
> static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
> {
> int rc = 0;
> @@ -104,6 +124,7 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel)
> }
> }
>
> + dp_panel_read_psr_cap(panel);
> end:
> return rc;
> }
> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h
> index 9023e5b..631657a 100644
> --- a/drivers/gpu/drm/msm/dp/dp_panel.h
> +++ b/drivers/gpu/drm/msm/dp/dp_panel.h
> @@ -34,6 +34,11 @@ struct dp_panel_in {
> struct dp_catalog *catalog;
> };
>
> +struct dp_panel_psr {
> + u8 version;
> + u8 capabilities;
> +};
> +
> struct dp_panel {
> /* dpcd raw data */
> u8 dpcd[DP_RECEIVER_CAP_SIZE + 1];
> @@ -46,6 +51,7 @@ struct dp_panel {
> struct edid *edid;
> struct drm_connector *connector;
> struct dp_display_mode dp_mode;
> + struct dp_panel_psr psr_cap;
> bool video_test;
>
> u32 vic;
> diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
> index 2686028..7a0b052 100644
> --- a/drivers/gpu/drm/msm/dp/dp_reg.h
> +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
> @@ -22,6 +22,20 @@
> #define REG_DP_INTR_STATUS2 (0x00000024)
> #define REG_DP_INTR_STATUS3 (0x00000028)
>
> +#define REG_DP_INTR_STATUS4 (0x0000002C)
> +#define PSR_UPDATE_INT (0x00000001)
> +#define PSR_CAPTURE_INT (0x00000004)
> +#define PSR_EXIT_INT (0x00000010)
> +#define PSR_UPDATE_ERROR_INT (0x00000040)
> +#define PSR_WAKE_ERROR_INT (0x00000100)
> +
> +#define REG_DP_INTR_MASK4 (0x00000030)
> +#define PSR_UPDATE_MASK (0x00000001)
> +#define PSR_CAPTURE_MASK (0x00000002)
> +#define PSR_EXIT_MASK (0x00000004)
> +#define PSR_UPDATE_ERROR_MASK (0x00000008)
> +#define PSR_WAKE_ERROR_MASK (0x00000010)
> +
> #define REG_DP_DP_HPD_CTRL (0x00000000)
> #define DP_DP_HPD_CTRL_HPD_EN (0x00000001)
>
> @@ -164,6 +178,9 @@
> #define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094)
> #define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098)
>
> +#define REG_PSR_CONFIG (0x00000100)
> +#define REG_PSR_CMD (0x00000110)
> +
> #define MMSS_DP_PSR_CRC_RG (0x00000154)
> #define MMSS_DP_PSR_CRC_B (0x00000158)
>
> @@ -184,6 +201,8 @@
> #define MMSS_DP_AUDIO_STREAM_0 (0x00000240)
> #define MMSS_DP_AUDIO_STREAM_1 (0x00000244)
>
> +#define MMSS_DP_SDP_CFG3 (0x0000024c)
> +
> #define MMSS_DP_EXTENSION_0 (0x00000250)
> #define MMSS_DP_EXTENSION_1 (0x00000254)
> #define MMSS_DP_EXTENSION_2 (0x00000258)
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d7574e6..28e182b 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -400,6 +400,8 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_displa
>
> void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor);
>
> +void msm_dp_display_set_psr(struct msm_dp *dp, bool enter);
> +
> #else
> static inline int __init msm_dp_register(void)
> {
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-02-15 13:47 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-12 12:51 [v1 1/2] drm/msm/dp: Add basic PSR support for eDP Vinod Polimera
2022-02-12 12:51 ` [v1 2/2] drm/msm/disp/dpu1: Add PSR support for eDP interface in dpu driver Vinod Polimera
2022-02-12 13:56 ` Dmitry Baryshkov
2022-02-12 13:49 ` [v1 1/2] drm/msm/dp: Add basic PSR support for eDP Dmitry Baryshkov
2022-02-15 13:47 ` Dmitry Baryshkov
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