From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
To: Jitao Shi <jitao.shi@mediatek.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
DRI Development <dri-devel@lists.freedesktop.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
DTML <devicetree@vger.kernel.org>,
srv_heupstream <srv_heupstream@mediatek.com>,
huijuan.xie@mediatek.com, stonea168@163.com,
Cawa Cheng <cawa.cheng@mediatek.com>,
shuijing.li@mediatek.com,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
yingjoe.chen@mediatek.com, eddie.huang@mediatek.com,
Linux ARM <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] drm/mediatek: fine tune the data lane trail by project dts
Date: Thu, 18 Mar 2021 08:31:02 +0800 [thread overview]
Message-ID: <CAAOTY_--LQxwvnmWws23OkShBiQdxumoULoLTuHeXXMqZ6aW7g@mail.gmail.com> (raw)
In-Reply-To: <20210201034755.15793-1-jitao.shi@mediatek.com>
Hi, Jitao:
Jitao Shi <jitao.shi@mediatek.com> 於 2021年2月1日 週一 上午11:48寫道:
>
> Some panels or bridges require customized hs_da_trail time.
> So add a property in devicetree for this panels and bridges.
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 8c70ec39bfe1..6e7092fa2fee 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -194,6 +194,7 @@ struct mtk_dsi {
> struct clk *hs_clk;
>
> u32 data_rate;
> + u32 da_trail_delta;
>
> unsigned long mode_flags;
> enum mipi_dsi_pixel_format format;
> @@ -234,7 +235,7 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
> timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
> timing->da_hs_prepare;
> - timing->da_hs_trail = timing->da_hs_prepare + 1;
> + timing->da_hs_trail = timing->da_hs_prepare + 1 + dsi->da_trail_delta;
>
> timing->ta_go = 4 * timing->lpx - 2;
> timing->ta_sure = timing->lpx + 2;
> @@ -1094,6 +1095,13 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> goto err_unregister_host;
> }
>
> + ret = of_property_read_u32_index(dev->of_node, "da_trail_delta", 0,
> + &dsi->da_trail_delta);
This value depends on panel, so I think we should get some value from
panel's device node to calculate this value.
Regards,
Chun-Kuang.
> + if (ret) {
> + dev_info(dev, "Can't get da_trail_delta, keep it as 0: %d\n", ret);
> + dsi->da_trail_delta = 0;
> + }
> +
> comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
> if (comp_id < 0) {
> dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> --
> 2.12.5
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
prev parent reply other threads:[~2021-03-18 0:32 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 3:47 [PATCH] drm/mediatek: fine tune the data lane trail by project dts Jitao Shi
2021-02-03 4:02 ` Nicolas Boichat
2021-03-18 0:31 ` Chun-Kuang Hu [this message]
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