* Re: [PATCH v13 3/8] drm/mediatek: add mtk_dither_set_common() function
[not found] ` <20210129092209.2584718-4-hsinyi@chromium.org>
@ 2021-01-30 9:50 ` Chun-Kuang Hu
0 siblings, 0 replies; 9+ messages in thread
From: Chun-Kuang Hu @ 2021-01-30 9:50 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML,
Yongqiang Niu, David Airlie, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Hsin-Yi:
Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年1月29日 週五 下午5:23寫道：
>
> Current implementation of mtk_dither_set() cast dev data to
> struct mtk_ddp_comp_dev. But other devices with different dev data
> would also call this function.
>
> Separate necessary parameters out so other device components (dither,
> gamma) can call this function.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 4 +++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 27 ++++++++++++++-------
> 2 files changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 46d199b7b4a29..9e5537f76b22a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -17,6 +17,10 @@ void mtk_color_config(struct device *dev, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> void mtk_color_start(struct device *dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
> + unsigned int bpc, unsigned int cfg,
> + unsigned int dither_en, struct cmdq_pkt *cmdq_pkt);
> +
> void mtk_dpi_start(struct device *dev);
> void mtk_dpi_stop(struct device *dev);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 7b5293429426d..07804ab16f44d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -151,33 +151,42 @@ static void mtk_ddp_clk_disable(struct device *dev)
> clk_disable_unprepare(priv->clk);
> }
>
> -static void mtk_dither_set(struct device *dev, unsigned int bpc,
> - unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
>
> +void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
> + unsigned int bpc, unsigned int cfg,
> + unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
> +{
> /* If bpc equal to 0, the dithering function didn't be enabled */
> if (bpc == 0)
> return;
>
> if (bpc >= MTK_MIN_BPC) {
> - mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_5);
> - mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, DISP_DITHER_7);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5);
> + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
> DITHER_NEW_BIT_MODE,
> - &priv->cmdq_reg, priv->regs, DISP_DITHER_15);
> + cmdq_reg, regs, DISP_DITHER_15);
> mtk_ddp_write(cmdq_pkt,
> DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
> DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
> DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
> - &priv->cmdq_reg, priv->regs, DISP_DITHER_16);
> - mtk_ddp_write(cmdq_pkt, DISP_DITHERING, &priv->cmdq_reg, priv->regs, CFG);
> + cmdq_reg, regs, DISP_DITHER_16);
> + mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
> }
> }
>
> +static void mtk_dither_set(struct device *dev, unsigned int bpc,
> + unsigned int cfg, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, cfg,
> + DISP_DITHERING, cmdq_pkt);
> +}
> +
> static void mtk_od_config(struct device *dev, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> --
> 2.30.0.365.g02bc693789-goog
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v13 4/8] drm/mediatek: separate gamma module
[not found] ` <20210129092209.2584718-5-hsinyi@chromium.org>
@ 2021-01-30 10:05 ` Chun-Kuang Hu
0 siblings, 0 replies; 9+ messages in thread
From: Chun-Kuang Hu @ 2021-01-30 10:05 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML,
Yongqiang Niu, David Airlie, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Hsin-Yi:
Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年1月29日 週五 下午5:23寫道：
>
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> mt8183 gamma module will different with mt8173
> separate gamma for add private data
After I clean up all checkpatch error, applied to mediatek-drm-next
[1]. Remember to clean up all checkpatch error before send out
patches.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 10 +
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 191 ++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 71 ++------
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 217 insertions(+), 61 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_gamma.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 01d06332f7679..b64674b944860 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -1,6 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0
>
> mediatek-drm-y := mtk_disp_color.o \
> + mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 9e5537f76b22a..02191010699f8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -27,6 +27,16 @@ void mtk_dpi_stop(struct device *dev);
> void mtk_dsi_ddp_start(struct device *dev);
> void mtk_dsi_ddp_stop(struct device *dev);
>
> +int mtk_gamma_clk_enable(struct device *dev);
> +void mtk_gamma_clk_disable(struct device *dev);
> +void mtk_gamma_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state);
> +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
> +void mtk_gamma_start(struct device *dev);
> +void mtk_gamma_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> new file mode 100644
> index 0000000000000..6b520807921e3
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -0,0 +1,191 @@
> +/*
> + * SPDX-License-Identifier:
> + *
> + * Copyright (c) 2020 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_GAMMA_EN 0x0000
> +#define GAMMA_EN BIT(0)
> +#define DISP_GAMMA_CFG 0x0020
> +#define GAMMA_LUT_EN BIT(1)
> +#define GAMMA_DITHERING BIT(2)
> +#define DISP_GAMMA_SIZE 0x0030
> +#define DISP_GAMMA_LUT 0x0700
> +
> +#define LUT_10BIT_MASK 0x03ff
> +
> +struct mtk_disp_gamma_data {
> + u32 reserved;
> +};
> +
> +/**
> + * struct mtk_disp_gamma - DISP_GAMMA driver structure
> + * @ddp_comp - structure containing type enum and hardware resources
> + * @crtc - associated crtc to report irq events to
> + */
> +struct mtk_disp_gamma {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_gamma_data *data;
> +};
> +
> +int mtk_gamma_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(gamma->clk);
> +}
> +
> +void mtk_gamma_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(gamma->clk);
> +}
> +
> +void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state)
> +{
> + unsigned int i, reg;
> + struct drm_color_lut *lut;
> + void __iomem *lut_base;
> + u32 word;
> +
> + if (state->gamma_lut) {
> + reg = readl(regs + DISP_GAMMA_CFG);
> + reg = reg | GAMMA_LUT_EN;
> + writel(reg, regs + DISP_GAMMA_CFG);
> + lut_base = regs + DISP_GAMMA_LUT;
> + lut = (struct drm_color_lut *)state->gamma_lut->data;
> + for (i = 0; i < MTK_LUT_SIZE; i++) {
> + word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
> + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
> + ((lut[i].blue >> 6) & LUT_10BIT_MASK);
> + writel(word, (lut_base + i * 4));
> + }
> + }
> +}
> +
> +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + mtk_gamma_set_common(gamma->regs, state);
> +}
> +
> +void mtk_gamma_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs,
> + DISP_GAMMA_SIZE);
> + mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG,
> + GAMMA_DITHERING, cmdq_pkt);
> +}
> +
> +void mtk_gamma_start(struct device *dev)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + writel(GAMMA_EN, gamma->regs + DISP_GAMMA_EN);
> +}
> +
> +void mtk_gamma_stop(struct device *dev)
> +{
> + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev);
> +
> + writel_relaxed(0x0, gamma->regs + DISP_GAMMA_EN);
> +}
> +
> +static int mtk_disp_gamma_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_gamma_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_gamma_component_ops = {
> + .bind = mtk_disp_gamma_bind,
> + .unbind = mtk_disp_gamma_unbind,
> +};
> +
> +static int mtk_disp_gamma_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_disp_gamma *priv;
> + struct resource *res;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get gamma clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to ioremap gamma\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + priv->data = of_device_get_match_data(dev);
> + platform_set_drvdata(pdev, priv);
> +
> + ret = component_add(dev, &mtk_disp_gamma_component_ops);
> + if (ret)
> + dev_err(dev, "Failed to add component: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int mtk_disp_gamma_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_gamma_component_ops);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8173-disp-gamma"},
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
> +
> +struct platform_driver mtk_disp_gamma_driver = {
> + .probe = mtk_disp_gamma_probe,
> + .remove = mtk_disp_gamma_remove,
> + .driver = {
> + .name = "mediatek-disp-gamma",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_gamma_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 07804ab16f44d..ac2cb25620357 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -55,11 +55,6 @@
> #define DITHER_RELAY_MODE BIT(0)
> #define DISP_DITHER_SIZE 0x0030
>
> -#define DISP_GAMMA_EN 0x0000
> -#define DISP_GAMMA_CFG 0x0020
> -#define DISP_GAMMA_SIZE 0x0030
> -#define DISP_GAMMA_LUT 0x0700
> -
> #define LUT_10BIT_MASK 0x03ff
>
> #define OD_RELAYMODE BIT(0)
> @@ -68,9 +63,6 @@
>
> #define AAL_EN BIT(0)
>
> -#define GAMMA_EN BIT(0)
> -#define GAMMA_LUT_EN BIT(1)
> -
> #define DISP_DITHERING BIT(2)
> #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
> #define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
> @@ -151,7 +143,6 @@ static void mtk_ddp_clk_disable(struct device *dev)
> clk_disable_unprepare(priv->clk);
> }
>
> -
> void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
> unsigned int bpc, unsigned int cfg,
> unsigned int dither_en, struct cmdq_pkt *cmdq_pkt)
> @@ -221,6 +212,13 @@ static void mtk_aal_config(struct device *dev, unsigned int w,
> mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_AAL_SIZE);
> }
>
> +static void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state)
> +{
> + struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> +
> + mtk_gamma_set_common(priv->regs, state);
> +}
> +
> static void mtk_aal_start(struct device *dev)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> @@ -335,58 +333,10 @@ static void mtk_dither_stop(struct device *dev)
> writel_relaxed(0x0, priv->regs + DISP_DITHER_EN);
> }
>
> -static void mtk_gamma_config(struct device *dev, unsigned int w,
> - unsigned int h, unsigned int vrefresh,
> - unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_GAMMA_SIZE);
> - mtk_dither_set(dev, bpc, DISP_GAMMA_CFG, cmdq_pkt);
> -}
> -
> -static void mtk_gamma_start(struct device *dev)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> - writel(GAMMA_EN, priv->regs + DISP_GAMMA_EN);
> -}
> -
> -static void mtk_gamma_stop(struct device *dev)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> - writel_relaxed(0x0, priv->regs + DISP_GAMMA_EN);
> -}
> -
> -static void mtk_gamma_set(struct device *dev,
> - struct drm_crtc_state *state)
> -{
> - struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> - unsigned int i, reg;
> - struct drm_color_lut *lut;
> - void __iomem *lut_base;
> - u32 word;
> -
> - if (state->gamma_lut) {
> - reg = readl(priv->regs + DISP_GAMMA_CFG);
> - reg = reg | GAMMA_LUT_EN;
> - writel(reg, priv->regs + DISP_GAMMA_CFG);
> - lut_base = priv->regs + DISP_GAMMA_LUT;
> - lut = (struct drm_color_lut *)state->gamma_lut->data;
> - for (i = 0; i < MTK_LUT_SIZE; i++) {
> - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
> - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
> - ((lut[i].blue >> 6) & LUT_10BIT_MASK);
> - writel(word, (lut_base + i * 4));
> - }
> - }
> -}
> -
> static const struct mtk_ddp_comp_funcs ddp_aal = {
> .clk_enable = mtk_ddp_clk_enable,
> .clk_disable = mtk_ddp_clk_disable,
> - .gamma_set = mtk_gamma_set,
> + .gamma_set = mtk_aal_gamma_set,
> .config = mtk_aal_config,
> .start = mtk_aal_start,
> .stop = mtk_aal_stop,
> @@ -427,8 +377,8 @@ static const struct mtk_ddp_comp_funcs ddp_dsi = {
> };
>
> static const struct mtk_ddp_comp_funcs ddp_gamma = {
> - .clk_enable = mtk_ddp_clk_enable,
> - .clk_disable = mtk_ddp_clk_disable,
> + .clk_enable = mtk_gamma_clk_enable,
> + .clk_disable = mtk_gamma_clk_disable,
> .gamma_set = mtk_gamma_set,
> .config = mtk_gamma_config,
> .start = mtk_gamma_start,
> @@ -644,6 +594,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
>
> if (type == MTK_DISP_BLS ||
> type == MTK_DISP_COLOR ||
> + type == MTK_DISP_GAMMA ||
> type == MTK_DPI ||
> type == MTK_DSI ||
> type == MTK_DISP_OVL ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 5d39dd54255d1..279d3e6f11563 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -486,11 +486,12 @@ static int mtk_drm_probe(struct platform_device *pdev)
> private->comp_node[comp_id] = of_node_get(node);
>
> /*
> - * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have
> + * Currently only the COLOR, GAMMA, OVL, RDMA, DSI, and DPI blocks have
> * separate component platform drivers and initialize their own
> * DDP component structure. The others are initialized here.
> */
> if (comp_type == MTK_DISP_COLOR ||
> + comp_type == MTK_DISP_GAMMA ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> comp_type == MTK_DISP_RDMA ||
> @@ -589,6 +590,7 @@ static struct platform_driver mtk_drm_platform_driver = {
>
> static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_disp_color_driver,
> + &mtk_disp_gamma_driver,
> &mtk_disp_ovl_driver,
> &mtk_disp_rdma_driver,
> &mtk_dpi_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index e8238fa4aa2ac..0e54e3d51014a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -47,6 +47,7 @@ struct mtk_drm_private {
> };
>
> extern struct platform_driver mtk_disp_color_driver;
> +extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> extern struct platform_driver mtk_disp_rdma_driver;
> extern struct platform_driver mtk_dpi_driver;
> --
> 2.30.0.365.g02bc693789-goog
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v13 5/8] drm/mediatek: add has_dither private data for gamma
[not found] ` <20210129092209.2584718-6-hsinyi@chromium.org>
@ 2021-01-30 10:12 ` Chun-Kuang Hu
0 siblings, 0 replies; 9+ messages in thread
From: Chun-Kuang Hu @ 2021-01-30 10:12 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML,
Yongqiang Niu, David Airlie, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Hsin-Yi:
Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年1月29日 週五 下午5:23寫道：
>
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Not all SoC has dither function in gamma module.
> Add private data to control this function setting.
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index 6b520807921e3..5092a27ccc28b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -27,7 +27,7 @@
> #define LUT_10BIT_MASK 0x03ff
>
> struct mtk_disp_gamma_data {
> - u32 reserved;
> + bool has_dither;
> };
>
> /**
> @@ -93,8 +93,9 @@ void mtk_gamma_config(struct device *dev, unsigned int w,
>
> mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs,
> DISP_GAMMA_SIZE);
> - mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG,
> - GAMMA_DITHERING, cmdq_pkt);
> + if (gamma->data && gamma->data->has_dither)
> + mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc,
> + DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt);
> }
>
> void mtk_gamma_start(struct device *dev)
> @@ -174,8 +175,13 @@ static int mtk_disp_gamma_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = {
> + .has_dither = true,
> +};
> +
> static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
> - { .compatible = "mediatek,mt8173-disp-gamma"},
> + { .compatible = "mediatek,mt8173-disp-gamma",
> + .data = &mt8173_gamma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
> --
> 2.30.0.365.g02bc693789-goog
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v13 8/8] drm/mediatek: add support for mediatek SOC MT8183
[not found] ` <20210129092209.2584718-9-hsinyi@chromium.org>
@ 2021-01-30 10:47 ` Chun-Kuang Hu
0 siblings, 0 replies; 9+ messages in thread
From: Chun-Kuang Hu @ 2021-01-30 10:47 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML,
Yongqiang Niu, David Airlie, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Hsin-Yi:
Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年1月29日 週五 下午5:23寫道：
>
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> 1. add ovl private data
> 2. add rdma private data
> 3. add gamma privte data
> 4. add main and external path module for crtc create
Applied to mediatek-drm-next [1], thanks.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next
Regards,
Chun-Kuang.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 45 +++++++++++++++++++++++
> 4 files changed, 70 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> index 5092a27ccc28b..7121d75a06bdc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c
> @@ -182,6 +182,7 @@ static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = {
> static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = {
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = &mt8173_gamma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-gamma"},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 1c295c58a5e82..da7e38a28759b 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -424,11 +424,29 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
> .fmt_rgb565_is_0 = true,
> };
>
> +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 4,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 2,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = &mt2701_ovl_driver_data},
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = &mt8173_ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl",
> + .data = &mt8183_ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> + .data = &mt8183_ovl_2l_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index b84004394970f..728aaadfea8cf 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -351,11 +351,17 @@ static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
> .fifo_size = SZ_8K,
> };
>
> +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
> + .fifo_size = 5 * SZ_1K,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = &mt2701_rdma_driver_data},
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = &mt8173_rdma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-rdma",
> + .data = &mt8183_rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 279d3e6f11563..486e73e675ad5 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -129,6 +129,24 @@ static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_OVL_2L0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSI0,
> +};
> +
> +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
> + DDP_COMPONENT_OVL_2L1,
> + DDP_COMPONENT_RDMA1,
> + DDP_COMPONENT_DPI0,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -161,6 +179,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> + .main_path = mt8183_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
> + .ext_path = mt8183_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -375,12 +400,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8183-disp-ovl",
> + .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> + .data = (void *)MTK_DISP_OVL_2L },
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8183-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-wdma",
> .data = (void *)MTK_DISP_WDMA },
> + { .compatible = "mediatek,mt8183-disp-ccorr",
> + .data = (void *)MTK_DISP_CCORR },
> { .compatible = "mediatek,mt2701-disp-color",
> .data = (void *)MTK_DISP_COLOR },
> { .compatible = "mediatek,mt8173-disp-color",
> @@ -389,22 +422,32 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_AAL},
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> + { .compatible = "mediatek,mt8183-disp-gamma",
> + .data = (void *)MTK_DISP_GAMMA, },
> + { .compatible = "mediatek,mt8183-disp-dither",
> + .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt2701-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8173-dsi",
> .data = (void *)MTK_DSI },
> + { .compatible = "mediatek,mt8183-dsi",
> + .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt2701-dpi",
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8173-dpi",
> .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt8183-dpi",
> + .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt2701-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2712-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8173-disp-pwm",
> @@ -423,6 +466,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
> .data = &mt2712_mmsys_driver_data},
> { .compatible = "mediatek,mt8173-mmsys",
> .data = &mt8173_mmsys_driver_data},
> + { .compatible = "mediatek,mt8183-mmsys",
> + .data = &mt8183_mmsys_driver_data},
> { }
> };
>
> --
> 2.30.0.365.g02bc693789-goog
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v13 6/8] drm/mediatek: enable dither function
[not found] ` <20210129092209.2584718-7-hsinyi@chromium.org>
@ 2021-01-31 3:39 ` Chun-Kuang Hu
2021-01-31 5:12 ` Hsin-Yi Wang
0 siblings, 1 reply; 9+ messages in thread
From: Chun-Kuang Hu @ 2021-01-31 3:39 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML,
Yongqiang Niu, David Airlie, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi, Hsin-Yi:
Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年1月29日 週五 下午5:23寫道：
>
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Enable dither function to improve the display quality for dither
> supported bpc 4, 6, 8. For not supported bpc, use relay mode.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index ac2cb25620357..5761dd15eedf2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -53,6 +53,7 @@
> #define DITHER_EN BIT(0)
> #define DISP_DITHER_CFG 0x0020
> #define DITHER_RELAY_MODE BIT(0)
> +#define DITHER_ENGINE_EN BIT(1)
> #define DISP_DITHER_SIZE 0x0030
>
> #define LUT_10BIT_MASK 0x03ff
> @@ -314,9 +315,17 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> -
> - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> + bool valid_bpc = (bpc == 4 || bpc == 6 || bpc == 8);
> +
> + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> + DISP_DITHER_SIZE);
> + if (valid_bpc)
> + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> + DISP_DITHER_CFG, DITHER_ENGINE_EN,
> + cmdq_pkt);
> + else
> + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> + priv->regs, DISP_DITHER_CFG);
od has relay mode,
static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
}
and it does not check valid bpc (I think drm core already set bpc to
4, 6, 8 or 0), so align implementation of mtk_dither_config() with
mtk_od_config().
gamma also has relay mode (refer to [1] page 689), but we need to
enable gamma's gamma function, so we do not set gamma to relay mode.
So I think maybe we could implement mtk_dither_config() as:
mtk_dither_config()
{
mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg,
priv->regs, DISP_DITHER_SIZE);
mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
priv->regs, DISP_DITHER_CFG);
mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
DISP_DITHER_CFG, DITHER_ENGINE_EN, cmdq_pkt);
}
[1] https://www.96boards.org/documentation/consumer/mediatekx20/additional-docs/docs/MT6797_Register_Table_Part_2.pdf
Regards,
Chun-Kuang.
> }
>
> static void mtk_dither_start(struct device *dev)
> --
> 2.30.0.365.g02bc693789-goog
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v13 6/8] drm/mediatek: enable dither function
2021-01-31 3:39 ` [PATCH v13 6/8] drm/mediatek: enable dither function Chun-Kuang Hu
@ 2021-01-31 5:12 ` Hsin-Yi Wang
0 siblings, 0 replies; 9+ messages in thread
From: Hsin-Yi Wang @ 2021-01-31 5:12 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, DTML,
Yongqiang Niu, David Airlie, linux-kernel, DRI Development,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
On Sun, Jan 31, 2021 at 11:40 AM Chun-Kuang Hu <chunkuang.hu@kernel.org> wrote:
>
> Hi, Hsin-Yi:
>
> Hsin-Yi Wang <hsinyi@chromium.org> 於 2021年1月29日 週五 下午5:23寫道：
> >
> > From: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >
> > Enable dither function to improve the display quality for dither
> > supported bpc 4, 6, 8. For not supported bpc, use relay mode.
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 ++++++++++++---
> > 1 file changed, 12 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index ac2cb25620357..5761dd15eedf2 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -53,6 +53,7 @@
> > #define DITHER_EN BIT(0)
> > #define DISP_DITHER_CFG 0x0020
> > #define DITHER_RELAY_MODE BIT(0)
> > +#define DITHER_ENGINE_EN BIT(1)
> > #define DISP_DITHER_SIZE 0x0030
> >
> > #define LUT_10BIT_MASK 0x03ff
> > @@ -314,9 +315,17 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > {
> > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > -
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> > + bool valid_bpc = (bpc == 4 || bpc == 6 || bpc == 8);
> > +
> > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> > + DISP_DITHER_SIZE);
> > + if (valid_bpc)
> > + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > + DISP_DITHER_CFG, DITHER_ENGINE_EN,
> > + cmdq_pkt);
> > + else
> > + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> > + priv->regs, DISP_DITHER_CFG);
>
> od has relay mode,
>
> static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
> unsigned int h, unsigned int vrefresh,
> unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> {
> mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
> mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
> mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
> }
>
> and it does not check valid bpc (I think drm core already set bpc to
> 4, 6, 8 or 0), so align implementation of mtk_dither_config() with
> mtk_od_config().
> gamma also has relay mode (refer to [1] page 689), but we need to
> enable gamma's gamma function, so we do not set gamma to relay mode.
> So I think maybe we could implement mtk_dither_config() as:
>
> mtk_dither_config()
> {
> mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg,
> priv->regs, DISP_DITHER_SIZE);
> mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> priv->regs, DISP_DITHER_CFG);
> mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> DISP_DITHER_CFG, DITHER_ENGINE_EN, cmdq_pkt);
> }
>
> [1] https://www.96boards.org/documentation/consumer/mediatekx20/additional-docs/docs/MT6797_Register_Table_Part_2.pdf
>
> Regards,
> Chun-Kuang.
>
Hi CK,
I send the patch here:
https://patchwork.kernel.org/project/linux-mediatek/patch/20210131051058.3407985-1-hsinyi@chromium.org/
as others are already merged to the tree.
Thanks
> > }
> >
> > static void mtk_dither_start(struct device *dev)
> > --
> > 2.30.0.365.g02bc693789-goog
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183
[not found] ` <20210129092209.2584718-8-hsinyi@chromium.org>
@ 2021-02-09 14:48 ` Enric Balletbo Serra
2021-02-10 12:14 ` Matthias Brugger
2021-03-17 16:31 ` Matthias Brugger
1 sibling, 1 reply; 9+ messages in thread
From: Enric Balletbo Serra @ 2021-02-09 14:48 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: CK Hu, Philipp Zabel, Matthias Brugger, Mark Rutland, devicetree,
Yongqiang Niu, David Airlie, linux-kernel, dri-devel,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
Hi Hsin-Yi,
Thank you for your patch.
Missatge de Hsin-Yi Wang <hsinyi@chromium.org> del dia dv., 29 de gen.
2021 a les 10:23:
>
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Add mtk mutex support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
FWIW this patch is required to have the display working on the
Chromebook IdeaPad Duet, so
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Matthias, If I am not wrong, this patch is the only one that is not
applied for this series. I know that is too late for 5.12, but If
you're fine with it, could you pick this patch directly or do you
prefer a resend of this patch alone once you will start to accept
patches for the next release?
Thanks,
Enric
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..718a41beb6afb 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_MUTEX0_MOD0 0x30
> +#define MT8183_MUTEX0_SOF0 0x2c
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,11 @@
> #define MT2712_MUTEX_SOF_DSI3 6
> #define MT8167_MUTEX_SOF_DPI0 2
> #define MT8167_MUTEX_SOF_DPI1 3
> +#define MT8183_MUTEX_SOF_DSI0 1
> +#define MT8183_MUTEX_SOF_DPI0 2
> +
> +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8167_mutex_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = &mt8173_mutex_driver_data},
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = &mt8183_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
> --
> 2.30.0.365.g02bc693789-goog
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183
2021-02-09 14:48 ` [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183 Enric Balletbo Serra
@ 2021-02-10 12:14 ` Matthias Brugger
0 siblings, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2021-02-10 12:14 UTC (permalink / raw)
To: Enric Balletbo Serra, Hsin-Yi Wang
Cc: CK Hu, Philipp Zabel, Mark Rutland, devicetree, Yongqiang Niu,
David Airlie, linux-kernel, dri-devel,
moderated list:ARM/Mediatek SoC support, Daniel Vetter,
Linux ARM
On 09/02/2021 15:48, Enric Balletbo Serra wrote:
> Hi Hsin-Yi,
>
> Thank you for your patch.
>
> Missatge de Hsin-Yi Wang <hsinyi@chromium.org> del dia dv., 29 de gen.
> 2021 a les 10:23:
>>
>> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>>
>> Add mtk mutex support for MT8183 SoC.
>>
>> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
>> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
>> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>
> FWIW this patch is required to have the display working on the
> Chromebook IdeaPad Duet, so
>
> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>
> Matthias, If I am not wrong, this patch is the only one that is not
> applied for this series. I know that is too late for 5.12, but If
> you're fine with it, could you pick this patch directly or do you
> prefer a resend of this patch alone once you will start to accept
> patches for the next release?
This patch is based on top of a patch that's in CK's branch.
Let's wait for v5.12-rc1 then I'll take it. If I forget just ping me here/IRC
Regards,
Matthias
>
> Thanks,
> Enric
>
>> ---
>> drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++
>> 1 file changed, 50 insertions(+)
>>
>> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
>> index f531b119da7a9..718a41beb6afb 100644
>> --- a/drivers/soc/mediatek/mtk-mutex.c
>> +++ b/drivers/soc/mediatek/mtk-mutex.c
>> @@ -14,6 +14,8 @@
>>
>> #define MT2701_MUTEX0_MOD0 0x2c
>> #define MT2701_MUTEX0_SOF0 0x30
>> +#define MT8183_MUTEX0_MOD0 0x30
>> +#define MT8183_MUTEX0_SOF0 0x2c
>>
>> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
>> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
>> @@ -37,6 +39,18 @@
>> #define MT8167_MUTEX_MOD_DISP_DITHER 15
>> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>>
>> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
>> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
>> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
>> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
>> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
>> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
>> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
>> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
>> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
>> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
>> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17
>> +
>> #define MT8173_MUTEX_MOD_DISP_OVL0 11
>> #define MT8173_MUTEX_MOD_DISP_OVL1 12
>> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
>> @@ -87,6 +101,11 @@
>> #define MT2712_MUTEX_SOF_DSI3 6
>> #define MT8167_MUTEX_SOF_DPI0 2
>> #define MT8167_MUTEX_SOF_DPI1 3
>> +#define MT8183_MUTEX_SOF_DSI0 1
>> +#define MT8183_MUTEX_SOF_DPI0 2
>> +
>> +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
>> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
>>
>> struct mtk_mutex {
>> int id;
>> @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
>> };
>>
>> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
>> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
>> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
>> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
>> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
>> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
>> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
>> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
>> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
>> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
>> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
>> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
>> +};
>> +
>> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
>> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
>> @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
>> };
>>
>> +/* Add EOF setting so overlay hardware can receive frame done irq */
>> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
>> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
>> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
>> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
>> +};
>> +
>> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
>> .mutex_mod = mt2701_mutex_mod,
>> .mutex_sof = mt2712_mutex_sof,
>> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = {
>> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
>> };
>>
>> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
>> + .mutex_mod = mt8183_mutex_mod,
>> + .mutex_sof = mt8183_mutex_sof,
>> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
>> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
>> + .no_clk = true,
>> +};
>> +
>> struct mtk_mutex *mtk_mutex_get(struct device *dev)
>> {
>> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
>> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
>> .data = &mt8167_mutex_driver_data},
>> { .compatible = "mediatek,mt8173-disp-mutex",
>> .data = &mt8173_mutex_driver_data},
>> + { .compatible = "mediatek,mt8183-disp-mutex",
>> + .data = &mt8183_mutex_driver_data},
>> {},
>> };
>> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
>> --
>> 2.30.0.365.g02bc693789-goog
>>
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183
[not found] ` <20210129092209.2584718-8-hsinyi@chromium.org>
2021-02-09 14:48 ` [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183 Enric Balletbo Serra
@ 2021-03-17 16:31 ` Matthias Brugger
1 sibling, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2021-03-17 16:31 UTC (permalink / raw)
To: Hsin-Yi Wang, CK Hu, Philipp Zabel
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Yongqiang Niu
On 29/01/2021 10:22, Hsin-Yi Wang wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> Add mtk mutex support for MT8183 SoC.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 50 ++++++++++++++++++++++++++++++++
> 1 file changed, 50 insertions(+)
>
Applied to v5.12-next/soc
Thanks
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index f531b119da7a9..718a41beb6afb 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -14,6 +14,8 @@
>
> #define MT2701_MUTEX0_MOD0 0x2c
> #define MT2701_MUTEX0_SOF0 0x30
> +#define MT8183_MUTEX0_MOD0 0x30
> +#define MT8183_MUTEX0_SOF0 0x2c
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> @@ -37,6 +39,18 @@
> #define MT8167_MUTEX_MOD_DISP_DITHER 15
> #define MT8167_MUTEX_MOD_DISP_UFOE 16
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -87,6 +101,11 @@
> #define MT2712_MUTEX_SOF_DSI3 6
> #define MT8167_MUTEX_SOF_DPI0 2
> #define MT8167_MUTEX_SOF_DPI1 3
> +#define MT8183_MUTEX_SOF_DSI0 1
> +#define MT8183_MUTEX_SOF_DPI0 2
> +
> +#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
>
> struct mtk_mutex {
> int id;
> @@ -181,6 +200,20 @@ static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -198,6 +231,13 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
> };
>
> +/* Add EOF setting so overlay hardware can receive frame done irq */
> +static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -227,6 +267,14 @@ static const struct mtk_mutex_data mt8173_mutex_driver_data = {
> .mutex_sof_reg = MT2701_MUTEX0_SOF0,
> };
>
> +static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .no_clk = true,
> +};
> +
> struct mtk_mutex *mtk_mutex_get(struct device *dev)
> {
> struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> @@ -457,6 +505,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8167_mutex_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = &mt8173_mutex_driver_data},
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = &mt8183_mutex_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2021-03-17 16:32 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <20210129092209.2584718-1-hsinyi@chromium.org>
[not found] ` <20210129092209.2584718-4-hsinyi@chromium.org>
2021-01-30 9:50 ` [PATCH v13 3/8] drm/mediatek: add mtk_dither_set_common() function Chun-Kuang Hu
[not found] ` <20210129092209.2584718-5-hsinyi@chromium.org>
2021-01-30 10:05 ` [PATCH v13 4/8] drm/mediatek: separate gamma module Chun-Kuang Hu
[not found] ` <20210129092209.2584718-6-hsinyi@chromium.org>
2021-01-30 10:12 ` [PATCH v13 5/8] drm/mediatek: add has_dither private data for gamma Chun-Kuang Hu
[not found] ` <20210129092209.2584718-9-hsinyi@chromium.org>
2021-01-30 10:47 ` [PATCH v13 8/8] drm/mediatek: add support for mediatek SOC MT8183 Chun-Kuang Hu
[not found] ` <20210129092209.2584718-7-hsinyi@chromium.org>
2021-01-31 3:39 ` [PATCH v13 6/8] drm/mediatek: enable dither function Chun-Kuang Hu
2021-01-31 5:12 ` Hsin-Yi Wang
[not found] ` <20210129092209.2584718-8-hsinyi@chromium.org>
2021-02-09 14:48 ` [PATCH v13 7/8] soc: mediatek: add mtk mutex support for MT8183 Enric Balletbo Serra
2021-02-10 12:14 ` Matthias Brugger
2021-03-17 16:31 ` Matthias Brugger
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