[PATCH v2, 00/17] drm/mediatek: add support for mediatek SOC MT8192

[PATCH v2, 00/17] drm/mediatek: add support for mediatek SOC MT8192

[Yongqiang Niu]

This series are based on 5.10-rc1 and provid 17 patch
to support mediatek SOC MT8192

Changes in v2:
- base mmsys
https://patchwork.kernel.org/project/linux-mediatek/cover/1607506379-10998-1-git-send-email-yongqiang.niu@mediatek.com/
- base mt8192 gce dtbinding file
https://patchwork.kernel.org/project/linux-mediatek/patch/1607141728-17307-2-git-send-email-yongqiang.niu@mediatek.com/
- add dt-bindings description for post mask
- add dt-bindings description for mt8192 display
- fix some comment in v1
- add mt8192 mmsys function call

Changes in v1:
- add some more ddp component
- add mt8192 mmsys support
- add ovl mount on support
- add 2 more clock into mutex device
- fix ovl smi_id_en and fb null software bug
- fix ddp compoent size config bug
- add mt8192 drm support
- add ddp bypass shadow register function
- add 8192 dts description

Yongqiang Niu (17):
  dt-bindings: mediatek: add description for postmask
  dt-bindings: mediatek: add CLK_MM_DISP_CONFIG control description for
    mt8192 display
  dt-bindings: mediatek: add description for mt8192 display
  drm/mediatek: add component OVL_2L2
  drm/mediatek: add component POSTMASK
  drm/mediatek: add component RDMA4
  drm/mediatek: add disp config and mm 26mhz clock into mutex device
  drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase
  drm/mediatek: check if fb is null
  drm/mediatek: fix aal size config
  drm/mediatek: fix dither size config
  drm/mediatek: fix gamma size config
  drm/mediatek: fix ccorr size config
  soc: mediatek: mmsys: Use function call for setting mmsys ovl mout
    register
  soc: mediatek: mmsys: add mt8192 mmsys support
  drm/mediatek: add support for mediatek SOC MT8192
  arm64: dts: mt8192: add display node

 .../bindings/display/mediatek/mediatek,disp.txt    |   6 +-
 arch/arm64/boot/dts/mediatek/mt8192.dtsi           | 130 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_color.c          |   6 +
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c            |  34 +++++-
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c           |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c             |  84 +++++++++++--
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c        |  50 +++++++-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h        |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c             |  48 ++++++++
 drivers/soc/mediatek/mmsys/Makefile                |   1 +
 drivers/soc/mediatek/mmsys/mt8192-mmsys.c          | 119 +++++++++++++++++++
 drivers/soc/mediatek/mmsys/mtk-mmsys.c             |  18 +++
 include/linux/soc/mediatek/mtk-mmsys.h             |   7 ++
 13 files changed, 496 insertions(+), 14 deletions(-)
 create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c

-- 
1.8.1.1.dirty

[PATCH v2, 01/17] dt-bindings: mediatek: add description for postmask

[Yongqiang Niu]

add description for postmask

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index 5ca693a..1972fa7 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -37,6 +37,7 @@ Required properties (all function blocks):
 	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
 	"mediatek,<chip>-disp-gamma" 		- gamma correction
 	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
+	"mediatek,<chip>-disp-postmask" 	- post mask
 	"mediatek,<chip>-disp-split" 		- split stream to two encoders
 	"mediatek,<chip>-disp-ufoe"  		- data compression engine
 	"mediatek,<chip>-dsi"        		- DSI controller, see mediatek,dsi.txt
-- 
1.8.1.1.dirty

[PATCH v2, 02/17] dt-bindings: mediatek: add CLK_MM_DISP_CONFIG control description for mt8192 display

[Yongqiang Niu]

add CLK_MM_DISP_CONFIG control description for mt8192 displa

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index 1972fa7..dfbec76 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -54,6 +54,9 @@ Required properties (all function blocks):
   DPI controller nodes have multiple clock inputs. These are documented in
   mediatek,dsi.txt and mediatek,dpi.txt, respectively.
   An exception is that the mt8183 mutex is always free running with no clocks property.
+  An exception is that the mt8192 display add 2 more clocks(CLK_MM_DISP_CONFIG, CLK_MM_26MHZ),
+  and these 2 clocks need enabled before display module work like mutex clock, so we add these
+  2 clocks controled same with mutex clock.
 
 Required properties (DMA function blocks):
 - compatible: Should be one of
-- 
1.8.1.1.dirty

[PATCH v2, 03/17] dt-bindings: mediatek: add description for mt8192 display

[Yongqiang Niu]

add description for mt8192 display

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index dfbec76..b4e62ae 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -44,7 +44,7 @@ Required properties (all function blocks):
 	"mediatek,<chip>-dpi"        		- DPI controller, see mediatek,dpi.txt
 	"mediatek,<chip>-disp-mutex" 		- display mutex
 	"mediatek,<chip>-disp-od"    		- overdrive
-  the supported chips are mt2701, mt7623, mt2712, mt8173 and mt8183.
+  the supported chips are mt2701, mt7623, mt2712, mt8173, mt8183 and mt8192.
 - reg: Physical base address and length of the function block register space
 - interrupts: The interrupt signal from the function block (required, except for
   merge and split function blocks).
-- 
1.8.1.1.dirty

[PATCH v2, 04/17] drm/mediatek: add component OVL_2L2

[Yongqiang Niu]

This patch add component OVL_2L2

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
 include/linux/soc/mediatek/mtk-mmsys.h      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 8eba44b..8938554 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -403,6 +403,7 @@ struct mtk_ddp_comp_match {
 	[DDP_COMPONENT_OVL1]	= { MTK_DISP_OVL,	1, NULL },
 	[DDP_COMPONENT_OVL_2L0]	= { MTK_DISP_OVL_2L,	0, NULL },
 	[DDP_COMPONENT_OVL_2L1]	= { MTK_DISP_OVL_2L,	1, NULL },
+	[DDP_COMPONENT_OVL_2L2]	= { MTK_DISP_OVL_2L,	2, NULL },
 	[DDP_COMPONENT_PWM0]	= { MTK_DISP_PWM,	0, NULL },
 	[DDP_COMPONENT_PWM1]	= { MTK_DISP_PWM,	1, NULL },
 	[DDP_COMPONENT_PWM2]	= { MTK_DISP_PWM,	2, NULL },
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4b6c514..42476c2 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_OVL0,
 	DDP_COMPONENT_OVL_2L0,
 	DDP_COMPONENT_OVL_2L1,
+	DDP_COMPONENT_OVL_2L2,
 	DDP_COMPONENT_OVL1,
 	DDP_COMPONENT_PWM0,
 	DDP_COMPONENT_PWM1,
-- 
1.8.1.1.dirty

[PATCH v2, 05/17] drm/mediatek: add component POSTMASK

[Yongqiang Niu]

This patch add component POSTMASK

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 31 +++++++++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 include/linux/soc/mediatek/mtk-mmsys.h      |  1 +
 3 files changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 8938554..4c91584 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -60,6 +60,10 @@
 #define DISP_GAMMA_SIZE				0x0030
 #define DISP_GAMMA_LUT				0x0700
 
+#define DISP_POSTMASK_EN			0x0000
+#define DISP_POSTMASK_CFG			0x0020
+#define DISP_POSTMASK_SIZE			0x0030
+
 #define LUT_10BIT_MASK				0x03ff
 
 #define OD_RELAYMODE				BIT(0)
@@ -321,6 +325,24 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
 	}
 }
 
+static void mtk_postmask_config(struct mtk_ddp_comp *comp, unsigned int w,
+			      unsigned int h, unsigned int vrefresh,
+			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_POSTMASK_SIZE);
+	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_POSTMASK_CFG);
+}
+
+static void mtk_postmask_start(struct mtk_ddp_comp *comp)
+{
+	writel(DITHER_EN, comp->regs + DISP_POSTMASK_EN);
+}
+
+static void mtk_postmask_stop(struct mtk_ddp_comp *comp)
+{
+	writel_relaxed(0x0, comp->regs + DISP_POSTMASK_EN);
+}
+
 static const struct mtk_ddp_comp_funcs ddp_aal = {
 	.gamma_set = mtk_gamma_set,
 	.config = mtk_aal_config,
@@ -348,6 +370,12 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_postmask = {
+	.config = mtk_postmask_config,
+	.start = mtk_postmask_start,
+	.stop = mtk_postmask_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.config = mtk_od_config,
 	.start = mtk_od_start,
@@ -374,6 +402,7 @@ static void mtk_gamma_set(struct mtk_ddp_comp *comp,
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_BLS] = "bls",
+	[MTK_DISP_POSTMASK] = "postmask",
 };
 
 struct mtk_ddp_comp_match {
@@ -404,6 +433,8 @@ struct mtk_ddp_comp_match {
 	[DDP_COMPONENT_OVL_2L0]	= { MTK_DISP_OVL_2L,	0, NULL },
 	[DDP_COMPONENT_OVL_2L1]	= { MTK_DISP_OVL_2L,	1, NULL },
 	[DDP_COMPONENT_OVL_2L2]	= { MTK_DISP_OVL_2L,	2, NULL },
+	[DDP_COMPONENT_POSTMASK0]
+				= { MTK_DISP_POSTMASK,	0, &ddp_postmask },
 	[DDP_COMPONENT_PWM0]	= { MTK_DISP_PWM,	0, NULL },
 	[DDP_COMPONENT_PWM1]	= { MTK_DISP_PWM,	1, NULL },
 	[DDP_COMPONENT_PWM2]	= { MTK_DISP_PWM,	2, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 5aa52b7..1a55496 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -29,6 +29,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_UFOE,
 	MTK_DSI,
 	MTK_DPI,
+	MTK_DISP_POSTMASK,
 	MTK_DISP_PWM,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 42476c2..09ee424 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -31,6 +31,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_OVL_2L1,
 	DDP_COMPONENT_OVL_2L2,
 	DDP_COMPONENT_OVL1,
+	DDP_COMPONENT_POSTMASK0,
 	DDP_COMPONENT_PWM0,
 	DDP_COMPONENT_PWM1,
 	DDP_COMPONENT_PWM2,
-- 
1.8.1.1.dirty

[PATCH v2, 06/17] drm/mediatek: add component RDMA4

[Yongqiang Niu]

This patch add component RDMA4

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
 include/linux/soc/mediatek/mtk-mmsys.h      | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 4c91584..be61d11 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -441,6 +441,7 @@ struct mtk_ddp_comp_match {
 	[DDP_COMPONENT_RDMA0]	= { MTK_DISP_RDMA,	0, NULL },
 	[DDP_COMPONENT_RDMA1]	= { MTK_DISP_RDMA,	1, NULL },
 	[DDP_COMPONENT_RDMA2]	= { MTK_DISP_RDMA,	2, NULL },
+	[DDP_COMPONENT_RDMA4]	= { MTK_DISP_RDMA,	4, NULL },
 	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
 	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
 	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 09ee424..aa4f60e 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_RDMA0,
 	DDP_COMPONENT_RDMA1,
 	DDP_COMPONENT_RDMA2,
+	DDP_COMPONENT_RDMA4,
 	DDP_COMPONENT_UFOE,
 	DDP_COMPONENT_WDMA0,
 	DDP_COMPONENT_WDMA1,
-- 
1.8.1.1.dirty

[PATCH v2, 07/17] drm/mediatek: add disp config and mm 26mhz clock into mutex device

[Yongqiang Niu]

there are 2 more clock need enable for display.
parser these clock when mutex device probe,
enable and disable when mutex on/off

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 49 ++++++++++++++++++++++++++++------
 1 file changed, 41 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 60788c1..de618a1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -118,7 +118,7 @@ struct mtk_ddp_data {
 
 struct mtk_ddp {
 	struct device			*dev;
-	struct clk			*clk;
+	struct clk			*clk[3];
 	void __iomem			*regs;
 	struct mtk_disp_mutex		mutex[10];
 	const struct mtk_ddp_data	*data;
@@ -257,14 +257,39 @@ int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex)
 {
 	struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
 					   mutex[mutex->id]);
-	return clk_prepare_enable(ddp->clk);
+	int ret;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
+		if (IS_ERR(ddp->clk[i]))
+			continue;
+		ret = clk_prepare_enable(ddp->clk[i]);
+		if (ret) {
+			pr_err("failed to enable clock, err %d. i:%d\n",
+				ret, i);
+			goto err;
+		}
+	}
+
+	return 0;
+
+err:
+	while (--i >= 0)
+		clk_disable_unprepare(ddp->clk[i]);
+	return ret;
 }
 
 void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex)
 {
 	struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
 					   mutex[mutex->id]);
-	clk_disable_unprepare(ddp->clk);
+	int i;
+
+	 for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
+		if (IS_ERR(ddp->clk[i]))
+			continue;
+		clk_disable_unprepare(ddp->clk[i]);
+	}
 }
 
 void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
@@ -415,11 +440,19 @@ static int mtk_ddp_probe(struct platform_device *pdev)
 	ddp->data = of_device_get_match_data(dev);
 
 	if (!ddp->data->no_clk) {
-		ddp->clk = devm_clk_get(dev, NULL);
-		if (IS_ERR(ddp->clk)) {
-			if (PTR_ERR(ddp->clk) != -EPROBE_DEFER)
-				dev_err(dev, "Failed to get clock\n");
-			return PTR_ERR(ddp->clk);
+		int ret;
+
+		for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
+			ddp->clk[i] = of_clk_get(dev->of_node, i);
+
+			if (IS_ERR(ddp->clk[i])) {
+				ret = PTR_ERR(ddp->clk[i]);
+				if (ret != EPROBE_DEFER)
+					dev_err(dev, "Failed to get clock %d\n",
+						ret);
+
+				return ret;
+			}
 		}
 	}
 
-- 
1.8.1.1.dirty

[PATCH v2, 08/17] drm/mediatek: enable OVL_LAYER_SMI_ID_EN for multi-layer usecase

[Yongqiang Niu]

enable OVL_LAYER_SMI_ID_EN for multi-layer usecase

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 8cf9f3b..97f8380 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -23,6 +23,7 @@
 #define DISP_REG_OVL_RST			0x0014
 #define DISP_REG_OVL_ROI_SIZE			0x0020
 #define DISP_REG_OVL_DATAPATH_CON		0x0024
+#define OVL_LAYER_SMI_ID_EN				BIT(0)
 #define OVL_BGCLR_SEL_IN				BIT(2)
 #define DISP_REG_OVL_ROI_BGCLR			0x0028
 #define DISP_REG_OVL_SRC_CON			0x002c
@@ -61,6 +62,7 @@ struct mtk_disp_ovl_data {
 	unsigned int gmc_bits;
 	unsigned int layer_nr;
 	bool fmt_rgb565_is_0;
+	bool smi_id_en;
 };
 
 /**
@@ -115,7 +117,17 @@ static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
 
 static void mtk_ovl_start(struct mtk_ddp_comp *comp)
 {
+	struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
+
 	writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
+
+	if(ovl->data->smi_id_en) {
+		unsigned int reg;
+
+		reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
+		reg = reg | OVL_LAYER_SMI_ID_EN;
+		writel_relaxed(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
+	}
 }
 
 static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
-- 
1.8.1.1.dirty

[PATCH v2, 09/17] drm/mediatek: check if fb is null

[Yongqiang Niu]

It's possible that state->base.fb is null. Add a check before access its
format.

Fixes: b6b1bb980ec4 ( drm/mediatek: Turn off Alpha bit when plane format has no alpha)
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 97f8380..47ae98c 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -278,7 +278,7 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
 	}
 
 	con = ovl_fmt_convert(ovl, fmt);
-	if (state->base.fb->format->has_alpha)
+	if (state->base.fb && state->base.fb->format->has_alpha)
 		con |= OVL_CON_AEN | OVL_CON_ALPHA;
 
 	if (pending->rotation & DRM_MODE_REFLECT_Y) {
-- 
1.8.1.1.dirty

[PATCH v2, 10/17] drm/mediatek: fix aal size config

[Yongqiang Niu]

fix aal size config

Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index be61d11..e7d481e0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -33,8 +33,13 @@
 #define DISP_REG_UFO_START			0x0000
 
 #define DISP_AAL_EN				0x0000
+#define DISP_AAL_CFG				0x0020
+#define AAL_RELAY_MODE					BIT(0)
+#define AAL_ENGINE_EN					BIT(1)
 #define DISP_AAL_SIZE				0x0030
 
+#define DISP_AAL_OUTPUT_SIZE			0x04d8
+
 #define DISP_CCORR_EN				0x0000
 #define CCORR_EN				BIT(0)
 #define DISP_CCORR_CFG				0x0020
@@ -184,7 +189,11 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
 			   unsigned int h, unsigned int vrefresh,
 			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 {
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_OUTPUT_SIZE);
+
+	mtk_ddp_write_mask(NULL, AAL_RELAY_MODE, comp, DISP_AAL_CFG,
+			   AAL_RELAY_MODE | AAL_ENGINE_EN);
 }
 
 static void mtk_aal_start(struct mtk_ddp_comp *comp)
-- 
1.8.1.1.dirty

[PATCH v2, 11/17] drm/mediatek: fix dither size config

[Yongqiang Niu]

fix dither size config

Fixes: 450aa87c7353 (drm/mediatek: add component DITHER)
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index e7d481e0..00d5687 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -279,7 +279,7 @@ static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
 			      unsigned int h, unsigned int vrefresh,
 			      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 {
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_DITHER_SIZE);
 	mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
 }
 
-- 
1.8.1.1.dirty

[PATCH v2, 12/17] drm/mediatek: fix gamma size config

[Yongqiang Niu]

fix gamma size config

Fixes: e0a5d3370245 (drm/mediatek: Add GAMMA engine basic function)
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 00d5687..52b6fc7 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -297,7 +297,7 @@ static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
 			     unsigned int h, unsigned int vrefresh,
 			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 {
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_GAMMA_SIZE);
 	mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
 }
 
-- 
1.8.1.1.dirty

[PATCH v2, 13/17] drm/mediatek: fix ccorr size config

[Yongqiang Niu]

fix ccorr size config

Fixes: cefb6abfcc1c (drm/mediatek: add ddp component CCORR)
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 52b6fc7..c11de66 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -210,7 +210,7 @@ static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
 			     unsigned int h, unsigned int vrefresh,
 			     unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 {
-	mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
+	mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_CCORR_SIZE);
 	mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, comp, DISP_CCORR_CFG);
 }
 
-- 
1.8.1.1.dirty

[PATCH v2, 14/17] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register

[Yongqiang Niu]

Use function call for setting mmsys ovl mout register

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/soc/mediatek/mmsys/mtk-mmsys.c | 18 ++++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h |  3 +++
 2 files changed, 21 insertions(+)

diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
index cb76e64..2558b42 100644
--- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
@@ -78,6 +78,15 @@ void mtk_mmsys_ddp_connect(struct device *dev,
 		reg = readl_relaxed(mmsys->regs + addr) | value;
 		writel_relaxed(reg, mmsys->regs + addr);
 	}
+
+	if (!funcs->ovl_mout_en)
+		return;
+
+	value = funcs->ovl_mout_en(cur, next, &addr);
+	if (value) {
+		reg = readl_relaxed(mmsys->regs + addr) | value;
+		writel_relaxed(reg, mmsys->regs + addr);
+	}
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
 
@@ -103,6 +112,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
 		reg = readl_relaxed(mmsys->regs + addr) & ~value;
 		writel_relaxed(reg, mmsys->regs + addr);
 	}
+
+	if (!funcs->ovl_mout_en)
+		return;
+
+	value = funcs->ovl_mout_en(cur, next, &addr);
+	if (value) {
+		reg = readl_relaxed(mmsys->regs + addr) & ~value;
+		writel_relaxed(reg, mmsys->regs + addr);
+	}
 }
 EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
 
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index aa4f60e..220203d 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs {
 	u32 (*mout_en)(enum mtk_ddp_comp_id cur,
 		       enum mtk_ddp_comp_id next,
 		       unsigned int *addr);
+	u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur,
+			   enum mtk_ddp_comp_id next,
+			   unsigned int *addr);
 	u32 (*sel_in)(enum mtk_ddp_comp_id cur,
 		      enum mtk_ddp_comp_id next,
 		      unsigned int *addr);
-- 
1.8.1.1.dirty

[PATCH v2, 15/17] soc: mediatek: mmsys: add mt8192 mmsys support

[Yongqiang Niu]

add mt8192 mmsys support

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/soc/mediatek/mmsys/Makefile       |   1 +
 drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h    |   1 +
 3 files changed, 121 insertions(+)
 create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c

diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
index 25eeb9e5..7508cd3 100644
--- a/drivers/soc/mediatek/mmsys/Makefile
+++ b/drivers/soc/mediatek/mmsys/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
+obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
 obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
new file mode 100644
index 0000000..79cb33f
--- /dev/null
+++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
@@ -0,0 +1,119 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#define MMSYS_OVL_MOUT_EN		0xf04
+#define DISP_OVL0_GO_BLEND			BIT(0)
+#define DISP_OVL0_GO_BG				BIT(1)
+#define DISP_OVL0_2L_GO_BLEND			BIT(2)
+#define DISP_OVL0_2L_GO_BG			BIT(3)
+#define DISP_OVL1_2L_MOUT_EN		0xf08
+#define OVL1_2L_MOUT_EN_RDMA1			BIT(4)
+#define DISP_OVL0_2L_MOUT_EN		0xf18
+#define DISP_OVL0_MOUT_EN		0xf1c
+#define OVL0_MOUT_EN_DISP_RDMA0			BIT(0)
+#define OVL0_MOUT_EN_OVL0_2L			BIT(4)
+#define DISP_RDMA0_SEL_IN		0xf2c
+#define RDMA0_SEL_IN_OVL0_2L			0x3
+#define DISP_RDMA0_SOUT_SEL		0xf30
+#define RDMA0_SOUT_COLOR0			0x1
+#define DISP_CCORR0_SOUT_SEL		0xf34
+#define CCORR0_SOUT_AAL0			0x1
+#define DISP_AAL0_SEL_IN		0xf38
+#define AAL0_SEL_IN_CCORR0			0x1
+#define DISP_DITHER0_MOUT_EN		0xf3c
+#define DITHER0_MOUT_DSI0			BIT(0)
+#define DISP_DSI0_SEL_IN		0xf40
+#define DSI0_SEL_IN_DITHER0			0x1
+#define DISP_OVL2_2L_MOUT_EN		0xf4c
+#define OVL2_2L_MOUT_RDMA4			BIT(0)
+
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+					  enum mtk_ddp_comp_id next,
+					  unsigned int *addr)
+{
+	unsigned int value;
+
+	if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+		*addr = DISP_OVL0_2L_MOUT_EN;
+		value = OVL0_MOUT_EN_DISP_RDMA0;
+	} else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
+		*addr = DISP_OVL2_2L_MOUT_EN;
+		value = OVL2_2L_MOUT_RDMA4;
+	} else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+		*addr = DISP_DITHER0_MOUT_EN;
+		value = DITHER0_MOUT_DSI0;
+	} else {
+		value = 0;
+	}
+
+	return value;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+					 enum mtk_ddp_comp_id next,
+					 unsigned int *addr)
+{
+	unsigned int value;
+
+	if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
+		*addr = DISP_RDMA0_SEL_IN;
+		value = RDMA0_SEL_IN_OVL0_2L;
+	} else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+		*addr = DISP_AAL0_SEL_IN;
+		value = AAL0_SEL_IN_CCORR0;
+	} else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
+		*addr = DISP_DSI0_SEL_IN;
+		value = DSI0_SEL_IN_DITHER0;
+	} else {
+		value = 0;
+	}
+
+	return value;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+				   enum mtk_ddp_comp_id cur,
+				   enum mtk_ddp_comp_id next)
+{
+	if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
+		writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
+	} else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
+		writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
+	}
+}
+
+static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur,
+					  enum mtk_ddp_comp_id next,
+					  unsigned int *addr)
+{
+	int value = -1;
+
+	*addr = MMSYS_OVL_MOUT_EN;
+
+	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
+		value = DISP_OVL0_GO_BG;
+	else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
+		value = DISP_OVL0_2L_GO_BG;
+	else if (cur == DDP_COMPONENT_OVL0)
+		value = DISP_OVL0_GO_BLEND;
+	else if (cur == DDP_COMPONENT_OVL_2L0)
+		value = DISP_OVL0_2L_GO_BLEND;
+	else
+		value = -1;
+
+	return value;
+}
+
+struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
+	.mout_en = mtk_mmsys_ddp_mout_en,
+	.ovl_mout_en = mtk_mmsys_ovl_mout_en,
+	.sel_in = mtk_mmsys_ddp_sel_in,
+	.sout_sel = mtk_mmsys_ddp_sout_sel,
+};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 220203d..efa07b9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs {
 
 extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
 extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
+extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
 
 void mtk_mmsys_ddp_connect(struct device *dev,
 			   enum mtk_ddp_comp_id cur,
-- 
1.8.1.1.dirty

[PATCH v2, 16/17] drm/mediatek: add support for mediatek SOC MT8192

[Yongqiang Niu]

add support for mediatek SOC MT8192

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_color.c |  6 ++++
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c   | 20 +++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c  |  6 ++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c    | 35 ++++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c    | 48 +++++++++++++++++++++++++++++++
 5 files changed, 115 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 3ae9c81..15389f8 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -152,11 +152,17 @@ static int mtk_disp_color_remove(struct platform_device *pdev)
 	.color_offset = DISP_COLOR_START_MT8173,
 };
 
+static const struct mtk_disp_color_data mt8192_color_driver_data = {
+	.color_offset = DISP_COLOR_START_MT8173,
+};
+
 static const struct of_device_id mtk_disp_color_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-color",
 	  .data = &mt2701_color_driver_data},
 	{ .compatible = "mediatek,mt8173-disp-color",
 	  .data = &mt8173_color_driver_data},
+	{ .compatible = "mediatek,mt8192-disp-color",
+	  .data = &mt8192_color_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_color_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 47ae98c..bcb455f 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -456,6 +456,22 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
 	.fmt_rgb565_is_0 = true,
 };
 
+static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
+	.addr = DISP_REG_OVL_ADDR_MT8173,
+	.gmc_bits = 10,
+	.layer_nr = 4,
+	.fmt_rgb565_is_0 = true,
+	.smi_id_en = true,
+};
+
+static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
+	.addr = DISP_REG_OVL_ADDR_MT8173,
+	.gmc_bits = 10,
+	.layer_nr = 2,
+	.fmt_rgb565_is_0 = true,
+	.smi_id_en = true,
+};
+
 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-ovl",
 	  .data = &mt2701_ovl_driver_data},
@@ -465,6 +481,10 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
 	  .data = &mt8183_ovl_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
 	  .data = &mt8183_ovl_2l_driver_data},
+	{ .compatible = "mediatek,mt8192-disp-ovl",
+	  .data = &mt8192_ovl_driver_data},
+	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
+	  .data = &mt8192_ovl_2l_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 86e77c2..2b79af0 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -363,6 +363,10 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
+	.fifo_size = 5 * SZ_1K,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -370,6 +374,8 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
 	  .data = &mt8173_rdma_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = &mt8183_rdma_driver_data},
+	{ .compatible = "mediatek,mt8192-disp-rdma",
+	  .data = &mt8192_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index de618a1..14105b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -27,6 +27,18 @@
 
 #define INT_MUTEX				BIT(1)
 
+#define MT8192_MUTEX_MOD_DISP_OVL0		0
+#define MT8192_MUTEX_MOD_DISP_OVL0_2L		1
+#define MT8192_MUTEX_MOD_DISP_RDMA0		2
+#define MT8192_MUTEX_MOD_DISP_COLOR0		4
+#define MT8192_MUTEX_MOD_DISP_CCORR0		5
+#define MT8192_MUTEX_MOD_DISP_AAL0		6
+#define MT8192_MUTEX_MOD_DISP_GAMMA0		7
+#define MT8192_MUTEX_MOD_DISP_POSTMASK0		8
+#define MT8192_MUTEX_MOD_DISP_DITHER0		9
+#define MT8192_MUTEX_MOD_DISP_OVL2_2L		16
+#define MT8192_MUTEX_MOD_DISP_RDMA4		17
+
 #define MT8183_MUTEX_MOD_DISP_RDMA0		0
 #define MT8183_MUTEX_MOD_DISP_RDMA1		1
 #define MT8183_MUTEX_MOD_DISP_OVL0		9
@@ -185,6 +197,20 @@ struct mtk_ddp {
 	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
+static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
+	[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
+	[DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
+	[DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
+};
+
 static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
 	[DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
@@ -229,6 +255,13 @@ struct mtk_ddp {
 	.mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
 };
 
+static const struct mtk_ddp_data mt8192_ddp_driver_data = {
+	.mutex_mod = mt8192_mutex_mod,
+	.mutex_sof = mt8183_mutex_sof,
+	.mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
+};
+
 struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
 {
 	struct mtk_ddp *ddp = dev_get_drvdata(dev);
@@ -482,6 +515,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
 	  .data = &mt8173_ddp_driver_data},
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = &mt8183_ddp_driver_data},
+	{ .compatible = "mediatek,mt8192-disp-mutex",
+	  .data = &mt8192_ddp_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a7e9f88..d372446 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -149,6 +149,25 @@
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_OVL_2L0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_POSTMASK0,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
+	DDP_COMPONENT_OVL_2L2,
+	DDP_COMPONENT_RDMA4,
+	DDP_COMPONENT_DPI0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -188,6 +207,13 @@
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+	.main_path = mt8192_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
+	.ext_path = mt8192_mtk_ddp_ext,
+	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -432,26 +458,42 @@ static void mtk_drm_unbind(struct device *dev)
 	  .data = (void *)MTK_DISP_OVL },
 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
 	  .data = (void *)MTK_DISP_OVL_2L },
+	{ .compatible = "mediatek,mt8192-disp-ovl",
+	  .data = (void *)MTK_DISP_OVL },
+	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
+	  .data = (void *)MTK_DISP_OVL_2L },
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8183-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8192-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
 	  .data = (void *)MTK_DISP_WDMA },
 	{ .compatible = "mediatek,mt8183-disp-ccorr",
 	  .data = (void *)MTK_DISP_CCORR },
+	{ .compatible = "mediatek,mt8192-disp-ccorr",
+	  .data = (void *)MTK_DISP_CCORR },
 	{ .compatible = "mediatek,mt2701-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-color",
 	  .data = (void *)MTK_DISP_COLOR },
+	{ .compatible = "mediatek,mt8192-disp-color",
+	  .data = (void *)MTK_DISP_COLOR },
 	{ .compatible = "mediatek,mt8173-disp-aal",
 	  .data = (void *)MTK_DISP_AAL},
+	{ .compatible = "mediatek,mt8192-disp-aal",
+	  .data = (void *)MTK_DISP_AAL},
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8192-disp-gamma",
+	  .data = (void *)MTK_DISP_GAMMA},
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8192-disp-dither",
+	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt2701-dsi",
@@ -474,12 +516,16 @@ static void mtk_drm_unbind(struct device *dev)
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8183-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8192-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2701-disp-pwm",
 	  .data = (void *)MTK_DISP_BLS },
 	{ .compatible = "mediatek,mt8173-disp-pwm",
 	  .data = (void *)MTK_DISP_PWM },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
+	{ .compatible = "mediatek,mt8192-disp-postmask",
+	  .data = (void *)MTK_DISP_POSTMASK },
 	{ }
 };
 
@@ -494,6 +540,8 @@ static void mtk_drm_unbind(struct device *dev)
 	  .data = &mt8173_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8183-mmsys",
 	  .data = &mt8183_mmsys_driver_data},
+	{ .compatible = "mediatek,mt8192-mmsys",
+	 .data = &mt8192_mmsys_driver_data},
 	{ }
 };
 
-- 
1.8.1.1.dirty

[PATCH v2, 17/17] arm64: dts: mt8192: add display node

[Yongqiang Niu]

add display node

Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8192.dtsi | 130 +++++++++++++++++++++++++++++++
 1 file changed, 130 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 7c0c233..da681b0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -17,6 +17,11 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		ovl_2l2 = &ovl_2l2;
+		rdma4 = &rdma4;
+	};
+
 	clk26m: oscillator0 {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
@@ -614,9 +619,134 @@
 		mmsys: syscon@14000000 {
 			compatible = "mediatek,mt8192-mmsys", "syscon";
 			reg = <0 0x14000000 0 0x1000>;
+			mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST 1>,
+				 <&gce 1 CMDQ_THR_PRIO_HIGHEST 1>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		mutex: mutex@14001000 {
+			compatible = "mediatek,mt8192-disp-mutex";
+			reg = <0 0x14001000 0 0x1000>;
+			interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_CONFIG>,
+			         <&mmsys CLK_MM_26MHZ>,
+			         <&mmsys CLK_MM_DISP_MUTEX0>;
+			mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
+					      <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
+		};
+
+		ovl0: ovl@14005000 {
+			compatible = "mediatek,mt8192-disp-ovl";
+			reg = <0 0x14005000 0 0x1000>;
+			interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0>;
+			//iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
+			//	 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+		};
+
+		ovl_2l0: ovl@14006000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14006000 0 0x1000>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
+			//iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
+			//	 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+		};
+
+		rdma0: rdma@14007000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14007000 0 0x1000>;
+			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+			//iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,rdma_fifo_size = <5120>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
+		};
+
+		color0: color@14009000 {
+			compatible = "mediatek,mt8192-disp-color",
+				     "mediatek,mt8173-disp-color";
+			reg = <0 0x14009000 0 0x1000>;
+			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>;
+		};
+
+		ccorr0: ccorr@1400a000 {
+			compatible = "mediatek,mt8192-disp-ccorr";
+			reg = <0 0x1400a000 0 0x1000>;
+			interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_CCORR0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>;
+		};
+
+		aal0: aal@1400b000 {
+			compatible = "mediatek,mt8192-disp-aal";
+			reg = <0 0x1400b000 0 0x1000>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_AAL0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
+		};
+
+		gamma0: gamma@1400c000 {
+			compatible = "mediatek,mt8192-disp-gamma";
+			reg = <0 0x1400c000 0 0x1000>;
+			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_GAMMA0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+		};
+
+		postmask0: postmask@1400d000 {
+			compatible = "mediatek,mt8192-disp-postmask";
+			reg = <0 0x1400d000 0 0x1000>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_POSTMASK0>;
+			//iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+		};
+
+		dither0: dither@1400e000 {
+			compatible = "mediatek,mt8192-disp-dither";
+			reg = <0 0x1400e000 0 0x1000>;
+			interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_DITHER0>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+		};
+
+		ovl_2l2: ovl@14014000 {
+			compatible = "mediatek,mt8192-disp-ovl-2l";
+			reg = <0 0x14014000 0 0x1000>;
+			interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_OVL2_2L>;
+			//iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
+			//	 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
+		};
+
+		rdma4: rdma@14015000 {
+			compatible = "mediatek,mt8192-disp-rdma";
+			reg = <0 0x14015000 0 0x1000>;
+			interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>;
+			//power-domains = <&scpsys MT8192_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_DISP_RDMA4>;
+			//iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA4>;
+			mediatek,rdma_fifo_size = <2048>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+		};
+
 		imgsys: syscon@15020000 {
 			compatible = "mediatek,mt8192-imgsys", "syscon";
 			reg = <0 0x15020000 0 0x1000>;
-- 
1.8.1.1.dirty

Re: [PATCH v2, 04/17] drm/mediatek: add component OVL_2L2

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:12寫道：
>
> This patch add component OVL_2L2

Break drm part and soc part into different patches.

Regards,
Chun-Kuang.

>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
>  include/linux/soc/mediatek/mtk-mmsys.h      | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 8eba44b..8938554 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -403,6 +403,7 @@ struct mtk_ddp_comp_match {
>         [DDP_COMPONENT_OVL1]    = { MTK_DISP_OVL,       1, NULL },
>         [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,    0, NULL },
>         [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,    1, NULL },
> +       [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,    2, NULL },
>         [DDP_COMPONENT_PWM0]    = { MTK_DISP_PWM,       0, NULL },
>         [DDP_COMPONENT_PWM1]    = { MTK_DISP_PWM,       1, NULL },
>         [DDP_COMPONENT_PWM2]    = { MTK_DISP_PWM,       2, NULL },
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 4b6c514..42476c2 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
>         DDP_COMPONENT_OVL0,
>         DDP_COMPONENT_OVL_2L0,
>         DDP_COMPONENT_OVL_2L1,
> +       DDP_COMPONENT_OVL_2L2,
>         DDP_COMPONENT_OVL1,
>         DDP_COMPONENT_PWM0,
>         DDP_COMPONENT_PWM1,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 03/17] dt-bindings: mediatek: add description for mt8192 display

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:12寫道：
>
> add description for mt8192 display

Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>

>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index dfbec76..b4e62ae 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -44,7 +44,7 @@ Required properties (all function blocks):
>         "mediatek,<chip>-dpi"                   - DPI controller, see mediatek,dpi.txt
>         "mediatek,<chip>-disp-mutex"            - display mutex
>         "mediatek,<chip>-disp-od"               - overdrive
> -  the supported chips are mt2701, mt7623, mt2712, mt8173 and mt8183.
> +  the supported chips are mt2701, mt7623, mt2712, mt8173, mt8183 and mt8192.
>  - reg: Physical base address and length of the function block register space
>  - interrupts: The interrupt signal from the function block (required, except for
>    merge and split function blocks).
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 15/17] soc: mediatek: mmsys: add mt8192 mmsys support

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:22寫道：
>
> add mt8192 mmsys support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/soc/mediatek/mmsys/Makefile       |   1 +
>  drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++
>  include/linux/soc/mediatek/mtk-mmsys.h    |   1 +
>  3 files changed, 121 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
>
> diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> index 25eeb9e5..7508cd3 100644
> --- a/drivers/soc/mediatek/mmsys/Makefile
> +++ b/drivers/soc/mediatek/mmsys/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0-only
>  obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
>  obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
>  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> new file mode 100644
> index 0000000..79cb33f
> --- /dev/null
> +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> @@ -0,0 +1,119 @@
> +// SPDX-License-Identifier: GPL-2.0
> +//
> +// Copyright (c) 2020 MediaTek Inc.
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#define MMSYS_OVL_MOUT_EN              0xf04
> +#define DISP_OVL0_GO_BLEND                     BIT(0)
> +#define DISP_OVL0_GO_BG                                BIT(1)
> +#define DISP_OVL0_2L_GO_BLEND                  BIT(2)
> +#define DISP_OVL0_2L_GO_BG                     BIT(3)
> +#define DISP_OVL1_2L_MOUT_EN           0xf08
> +#define OVL1_2L_MOUT_EN_RDMA1                  BIT(4)
> +#define DISP_OVL0_2L_MOUT_EN           0xf18
> +#define DISP_OVL0_MOUT_EN              0xf1c
> +#define OVL0_MOUT_EN_DISP_RDMA0                        BIT(0)
> +#define OVL0_MOUT_EN_OVL0_2L                   BIT(4)
> +#define DISP_RDMA0_SEL_IN              0xf2c
> +#define RDMA0_SEL_IN_OVL0_2L                   0x3
> +#define DISP_RDMA0_SOUT_SEL            0xf30
> +#define RDMA0_SOUT_COLOR0                      0x1
> +#define DISP_CCORR0_SOUT_SEL           0xf34
> +#define CCORR0_SOUT_AAL0                       0x1
> +#define DISP_AAL0_SEL_IN               0xf38
> +#define AAL0_SEL_IN_CCORR0                     0x1
> +#define DISP_DITHER0_MOUT_EN           0xf3c
> +#define DITHER0_MOUT_DSI0                      BIT(0)
> +#define DISP_DSI0_SEL_IN               0xf40
> +#define DSI0_SEL_IN_DITHER0                    0x1
> +#define DISP_OVL2_2L_MOUT_EN           0xf4c
> +#define OVL2_2L_MOUT_RDMA4                     BIT(0)
> +
> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> +                                         enum mtk_ddp_comp_id next,
> +                                         unsigned int *addr)
> +{
> +       unsigned int value;
> +
> +       if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> +               *addr = DISP_OVL0_2L_MOUT_EN;
> +               value = OVL0_MOUT_EN_DISP_RDMA0;
> +       } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
> +               *addr = DISP_OVL2_2L_MOUT_EN;
> +               value = OVL2_2L_MOUT_RDMA4;
> +       } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> +               *addr = DISP_DITHER0_MOUT_EN;
> +               value = DITHER0_MOUT_DSI0;
> +       } else {
> +               value = 0;
> +       }
> +
> +       return value;
> +}
> +
> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> +                                        enum mtk_ddp_comp_id next,
> +                                        unsigned int *addr)
> +{
> +       unsigned int value;
> +
> +       if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> +               *addr = DISP_RDMA0_SEL_IN;
> +               value = RDMA0_SEL_IN_OVL0_2L;
> +       } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> +               *addr = DISP_AAL0_SEL_IN;
> +               value = AAL0_SEL_IN_CCORR0;
> +       } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> +               *addr = DISP_DSI0_SEL_IN;
> +               value = DSI0_SEL_IN_DITHER0;
> +       } else {
> +               value = 0;
> +       }
> +
> +       return value;
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> +                                  enum mtk_ddp_comp_id cur,
> +                                  enum mtk_ddp_comp_id next)
> +{
> +       if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
> +               writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
> +       } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> +               writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
> +       }
> +}
> +
> +static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur,
> +                                         enum mtk_ddp_comp_id next,
> +                                         unsigned int *addr)
> +{
> +       int value = -1;
> +
> +       *addr = MMSYS_OVL_MOUT_EN;
> +
> +       if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
> +               value = DISP_OVL0_GO_BG;
> +       else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
> +               value = DISP_OVL0_2L_GO_BG;
> +       else if (cur == DDP_COMPONENT_OVL0)
> +               value = DISP_OVL0_GO_BLEND;
> +       else if (cur == DDP_COMPONENT_OVL_2L0)
> +               value = DISP_OVL0_2L_GO_BLEND;
> +       else
> +               value = -1;
> +
> +       return value;
> +}

I think you should squash mtk_mmsys_ovl_mout_en() with mtk_mmsys_ddp_mout_en().

Regards,
Chun-Kuang.

> +
> +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
> +       .mout_en = mtk_mmsys_ddp_mout_en,
> +       .ovl_mout_en = mtk_mmsys_ovl_mout_en,
> +       .sel_in = mtk_mmsys_ddp_sel_in,
> +       .sout_sel = mtk_mmsys_ddp_sout_sel,
> +};
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 220203d..efa07b9 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs {
>
>  extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
>  extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
> +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
>
>  void mtk_mmsys_ddp_connect(struct device *dev,
>                            enum mtk_ddp_comp_id cur,
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 15/17] soc: mediatek: mmsys: add mt8192 mmsys support

[Yongqiang Niu]

On Mon, 2020-12-14 at 00:02 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:22寫道：
> >
> > add mt8192 mmsys support
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/soc/mediatek/mmsys/Makefile       |   1 +
> >  drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++
> >  include/linux/soc/mediatek/mtk-mmsys.h    |   1 +
> >  3 files changed, 121 insertions(+)
> >  create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> >
> > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> > index 25eeb9e5..7508cd3 100644
> > --- a/drivers/soc/mediatek/mmsys/Makefile
> > +++ b/drivers/soc/mediatek/mmsys/Makefile
> > @@ -1,4 +1,5 @@
> >  # SPDX-License-Identifier: GPL-2.0-only
> >  obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
> >  obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
> > +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
> >  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> > new file mode 100644
> > index 0000000..79cb33f
> > --- /dev/null
> > +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> > @@ -0,0 +1,119 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +//
> > +// Copyright (c) 2020 MediaTek Inc.
> > +
> > +#include <linux/device.h>
> > +#include <linux/io.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#define MMSYS_OVL_MOUT_EN              0xf04
> > +#define DISP_OVL0_GO_BLEND                     BIT(0)
> > +#define DISP_OVL0_GO_BG                                BIT(1)
> > +#define DISP_OVL0_2L_GO_BLEND                  BIT(2)
> > +#define DISP_OVL0_2L_GO_BG                     BIT(3)
> > +#define DISP_OVL1_2L_MOUT_EN           0xf08
> > +#define OVL1_2L_MOUT_EN_RDMA1                  BIT(4)
> > +#define DISP_OVL0_2L_MOUT_EN           0xf18
> > +#define DISP_OVL0_MOUT_EN              0xf1c
> > +#define OVL0_MOUT_EN_DISP_RDMA0                        BIT(0)
> > +#define OVL0_MOUT_EN_OVL0_2L                   BIT(4)
> > +#define DISP_RDMA0_SEL_IN              0xf2c
> > +#define RDMA0_SEL_IN_OVL0_2L                   0x3
> > +#define DISP_RDMA0_SOUT_SEL            0xf30
> > +#define RDMA0_SOUT_COLOR0                      0x1
> > +#define DISP_CCORR0_SOUT_SEL           0xf34
> > +#define CCORR0_SOUT_AAL0                       0x1
> > +#define DISP_AAL0_SEL_IN               0xf38
> > +#define AAL0_SEL_IN_CCORR0                     0x1
> > +#define DISP_DITHER0_MOUT_EN           0xf3c
> > +#define DITHER0_MOUT_DSI0                      BIT(0)
> > +#define DISP_DSI0_SEL_IN               0xf40
> > +#define DSI0_SEL_IN_DITHER0                    0x1
> > +#define DISP_OVL2_2L_MOUT_EN           0xf4c
> > +#define OVL2_2L_MOUT_RDMA4                     BIT(0)
> > +
> > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > +                                         enum mtk_ddp_comp_id next,
> > +                                         unsigned int *addr)
> > +{
> > +       unsigned int value;
> > +
> > +       if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> > +               *addr = DISP_OVL0_2L_MOUT_EN;
> > +               value = OVL0_MOUT_EN_DISP_RDMA0;
> > +       } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
> > +               *addr = DISP_OVL2_2L_MOUT_EN;
> > +               value = OVL2_2L_MOUT_RDMA4;
> > +       } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> > +               *addr = DISP_DITHER0_MOUT_EN;
> > +               value = DITHER0_MOUT_DSI0;
> > +       } else {
> > +               value = 0;
> > +       }
> > +
> > +       return value;
> > +}
> > +
> > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > +                                        enum mtk_ddp_comp_id next,
> > +                                        unsigned int *addr)
> > +{
> > +       unsigned int value;
> > +
> > +       if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> > +               *addr = DISP_RDMA0_SEL_IN;
> > +               value = RDMA0_SEL_IN_OVL0_2L;
> > +       } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> > +               *addr = DISP_AAL0_SEL_IN;
> > +               value = AAL0_SEL_IN_CCORR0;
> > +       } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> > +               *addr = DISP_DSI0_SEL_IN;
> > +               value = DSI0_SEL_IN_DITHER0;
> > +       } else {
> > +               value = 0;
> > +       }
> > +
> > +       return value;
> > +}
> > +
> > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> > +                                  enum mtk_ddp_comp_id cur,
> > +                                  enum mtk_ddp_comp_id next)
> > +{
> > +       if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
> > +               writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
> > +       } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> > +               writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
> > +       }
> > +}
> > +
> > +static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur,
> > +                                         enum mtk_ddp_comp_id next,
> > +                                         unsigned int *addr)
> > +{
> > +       int value = -1;
> > +
> > +       *addr = MMSYS_OVL_MOUT_EN;
> > +
> > +       if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
> > +               value = DISP_OVL0_GO_BG;
> > +       else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
> > +               value = DISP_OVL0_2L_GO_BG;
> > +       else if (cur == DDP_COMPONENT_OVL0)
> > +               value = DISP_OVL0_GO_BLEND;
> > +       else if (cur == DDP_COMPONENT_OVL_2L0)
> > +               value = DISP_OVL0_2L_GO_BLEND;
> > +       else
> > +               value = -1;
> > +
> > +       return value;
> > +}
> 
> I think you should squash mtk_mmsys_ovl_mout_en() with mtk_mmsys_ddp_mout_en().
> 
> Regards,
> Chun-Kuang.

hi 

in soc mt8192,  ovl0_2l -> rdma0 usecase need set 2 register:
DISP_OVL0_2L_MOUT_EN and MMSYS_OVL_MOUT_EN,
'if-else' in mtk_mmsys_ddp_mout_en can not cover this case.

> 
> > +
> > +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
> > +       .mout_en = mtk_mmsys_ddp_mout_en,
> > +       .ovl_mout_en = mtk_mmsys_ovl_mout_en,
> > +       .sel_in = mtk_mmsys_ddp_sel_in,
> > +       .sout_sel = mtk_mmsys_ddp_sout_sel,
> > +};
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 220203d..efa07b9 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs {
> >
> >  extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
> >  extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
> > +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
> >
> >  void mtk_mmsys_ddp_connect(struct device *dev,
> >                            enum mtk_ddp_comp_id cur,
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 12/17] drm/mediatek: fix gamma size config

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:13寫道：
>
> fix gamma size config

I would like you to provide more information. The original code works
in mt8173, why do you modify this? The description may be something
like this:

According to data sheet, the width is in bits [31, 16] and height is
in bits [15, 0]. Even though wrong setting may works in some SoC such
as mt8173, but it does not work in mt8192.

Regards,
Chun-Kuang.

>
> Fixes: e0a5d3370245 (drm/mediatek: Add GAMMA engine basic function)
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 00d5687..52b6fc7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -297,7 +297,7 @@ static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
>                              unsigned int h, unsigned int vrefresh,
>                              unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
>  {
> -       mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_GAMMA_SIZE);
>         mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
>  }
>
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 07/17] drm/mediatek: add disp config and mm 26mhz clock into mutex device

[Nicolas Boichat]

On Sat, Dec 12, 2020 at 12:12 PM Yongqiang Niu
<yongqiang.niu@mediatek.com> wrote:
>
> there are 2 more clock need enable for display.
> parser these clock when mutex device probe,
> enable and disable when mutex on/off
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 49 ++++++++++++++++++++++++++++------
>  1 file changed, 41 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 60788c1..de618a1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -118,7 +118,7 @@ struct mtk_ddp_data {
>
>  struct mtk_ddp {
>         struct device                   *dev;
> -       struct clk                      *clk;
> +       struct clk                      *clk[3];
>         void __iomem                    *regs;
>         struct mtk_disp_mutex           mutex[10];
>         const struct mtk_ddp_data       *data;
> @@ -257,14 +257,39 @@ int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex)
>  {
>         struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
>                                            mutex[mutex->id]);
> -       return clk_prepare_enable(ddp->clk);
> +       int ret;
> +       int i;
> +
> +       for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
> +               if (IS_ERR(ddp->clk[i]))
> +                       continue;
> +               ret = clk_prepare_enable(ddp->clk[i]);
> +               if (ret) {
> +                       pr_err("failed to enable clock, err %d. i:%d\n",
> +                               ret, i);
> +                       goto err;
> +               }
> +       }
> +
> +       return 0;
> +
> +err:
> +       while (--i >= 0)
> +               clk_disable_unprepare(ddp->clk[i]);
> +       return ret;
>  }
>
>  void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex)
>  {
>         struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
>                                            mutex[mutex->id]);
> -       clk_disable_unprepare(ddp->clk);
> +       int i;
> +
> +        for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
> +               if (IS_ERR(ddp->clk[i]))
> +                       continue;
> +               clk_disable_unprepare(ddp->clk[i]);
> +       }
>  }
>
>  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> @@ -415,11 +440,19 @@ static int mtk_ddp_probe(struct platform_device *pdev)
>         ddp->data = of_device_get_match_data(dev);
>
>         if (!ddp->data->no_clk) {
> -               ddp->clk = devm_clk_get(dev, NULL);
> -               if (IS_ERR(ddp->clk)) {
> -                       if (PTR_ERR(ddp->clk) != -EPROBE_DEFER)
> -                               dev_err(dev, "Failed to get clock\n");
> -                       return PTR_ERR(ddp->clk);
> +               int ret;
> +
> +               for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
> +                       ddp->clk[i] = of_clk_get(dev->of_node, i);
> +
> +                       if (IS_ERR(ddp->clk[i])) {
> +                               ret = PTR_ERR(ddp->clk[i]);
> +                               if (ret != EPROBE_DEFER)
> +                                       dev_err(dev, "Failed to get clock %d\n",
> +                                               ret);
> +
> +                               return ret;
> +                       }

Use of_clk_bulk_get_all instead?

ddp->num_clks = of_clk_bulk_get_all(dev->of_node, &ddp->clks);
...

Then the calls above can be clk_bulk_enable/clk_bulk_disable using
num_clks and clks.


>                 }
>         }
>
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 14/17] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register

[Nicolas Boichat]

On Sat, Dec 12, 2020 at 12:13 PM Yongqiang Niu
<yongqiang.niu@mediatek.com> wrote:
>
> Use function call for setting mmsys ovl mout register
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 18 ++++++++++++++++++
>  include/linux/soc/mediatek/mtk-mmsys.h |  3 +++
>  2 files changed, 21 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> index cb76e64..2558b42 100644
> --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> @@ -78,6 +78,15 @@ void mtk_mmsys_ddp_connect(struct device *dev,
>                 reg = readl_relaxed(mmsys->regs + addr) | value;
>                 writel_relaxed(reg, mmsys->regs + addr);
>         }
> +
> +       if (!funcs->ovl_mout_en)
> +               return;
> +
> +       value = funcs->ovl_mout_en(cur, next, &addr);
> +       if (value) {
> +               reg = readl_relaxed(mmsys->regs + addr) | value;
> +               writel_relaxed(reg, mmsys->regs + addr);
> +       }

This is technically correct, but I'm afraid this may become and issue
later if we have another function like ovl_mout_en.

So maybe it's better to do:
if (funcs->ovl_mout_en) {
  value = funcs->ovl_mout_en(cur, next, &addr);
  ...
}

Or another option: Create a new function
static unsigned int mtk_mmsys_ovl_mout_en(...) {
   if (!funcs->ovl_mout_en)
      return 0;
}

and call that, following the same pattern as
mtk_mmsys_ddp_mout_en/mtk_mmsys_ddp_sel_in?

>  }
>  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>
> @@ -103,6 +112,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>                 reg = readl_relaxed(mmsys->regs + addr) & ~value;
>                 writel_relaxed(reg, mmsys->regs + addr);
>         }
> +
> +       if (!funcs->ovl_mout_en)
> +               return;
> +
> +       value = funcs->ovl_mout_en(cur, next, &addr);
> +       if (value) {
> +               reg = readl_relaxed(mmsys->regs + addr) & ~value;
> +               writel_relaxed(reg, mmsys->regs + addr);
> +       }
>  }
>  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index aa4f60e..220203d 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs {
>         u32 (*mout_en)(enum mtk_ddp_comp_id cur,
>                        enum mtk_ddp_comp_id next,
>                        unsigned int *addr);
> +       u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur,
> +                          enum mtk_ddp_comp_id next,
> +                          unsigned int *addr);
>         u32 (*sel_in)(enum mtk_ddp_comp_id cur,
>                       enum mtk_ddp_comp_id next,
>                       unsigned int *addr);
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 15/17] soc: mediatek: mmsys: add mt8192 mmsys support

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月14日 週一 上午8:39寫道：
>
> On Mon, 2020-12-14 at 00:02 +0800, Chun-Kuang Hu wrote:
> > Hi, Yongqiang:
> >
> > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:22寫道：
> > >
> > > add mt8192 mmsys support
> > >
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > >  drivers/soc/mediatek/mmsys/Makefile       |   1 +
> > >  drivers/soc/mediatek/mmsys/mt8192-mmsys.c | 119 ++++++++++++++++++++++++++++++
> > >  include/linux/soc/mediatek/mtk-mmsys.h    |   1 +
> > >  3 files changed, 121 insertions(+)
> > >  create mode 100644 drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> > >
> > > diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile
> > > index 25eeb9e5..7508cd3 100644
> > > --- a/drivers/soc/mediatek/mmsys/Makefile
> > > +++ b/drivers/soc/mediatek/mmsys/Makefile
> > > @@ -1,4 +1,5 @@
> > >  # SPDX-License-Identifier: GPL-2.0-only
> > >  obj-$(CONFIG_MTK_MMSYS) += mt2701-mmsys.o
> > >  obj-$(CONFIG_MTK_MMSYS) += mt8183-mmsys.o
> > > +obj-$(CONFIG_MTK_MMSYS) += mt8192-mmsys.o
> > >  obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> > > diff --git a/drivers/soc/mediatek/mmsys/mt8192-mmsys.c b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> > > new file mode 100644
> > > index 0000000..79cb33f
> > > --- /dev/null
> > > +++ b/drivers/soc/mediatek/mmsys/mt8192-mmsys.c
> > > @@ -0,0 +1,119 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +//
> > > +// Copyright (c) 2020 MediaTek Inc.
> > > +
> > > +#include <linux/device.h>
> > > +#include <linux/io.h>
> > > +#include <linux/of_device.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > > +
> > > +#define MMSYS_OVL_MOUT_EN              0xf04
> > > +#define DISP_OVL0_GO_BLEND                     BIT(0)
> > > +#define DISP_OVL0_GO_BG                                BIT(1)
> > > +#define DISP_OVL0_2L_GO_BLEND                  BIT(2)
> > > +#define DISP_OVL0_2L_GO_BG                     BIT(3)
> > > +#define DISP_OVL1_2L_MOUT_EN           0xf08
> > > +#define OVL1_2L_MOUT_EN_RDMA1                  BIT(4)
> > > +#define DISP_OVL0_2L_MOUT_EN           0xf18
> > > +#define DISP_OVL0_MOUT_EN              0xf1c
> > > +#define OVL0_MOUT_EN_DISP_RDMA0                        BIT(0)
> > > +#define OVL0_MOUT_EN_OVL0_2L                   BIT(4)
> > > +#define DISP_RDMA0_SEL_IN              0xf2c
> > > +#define RDMA0_SEL_IN_OVL0_2L                   0x3
> > > +#define DISP_RDMA0_SOUT_SEL            0xf30
> > > +#define RDMA0_SOUT_COLOR0                      0x1
> > > +#define DISP_CCORR0_SOUT_SEL           0xf34
> > > +#define CCORR0_SOUT_AAL0                       0x1
> > > +#define DISP_AAL0_SEL_IN               0xf38
> > > +#define AAL0_SEL_IN_CCORR0                     0x1
> > > +#define DISP_DITHER0_MOUT_EN           0xf3c
> > > +#define DITHER0_MOUT_DSI0                      BIT(0)
> > > +#define DISP_DSI0_SEL_IN               0xf40
> > > +#define DSI0_SEL_IN_DITHER0                    0x1
> > > +#define DISP_OVL2_2L_MOUT_EN           0xf4c
> > > +#define OVL2_2L_MOUT_RDMA4                     BIT(0)
> > > +
> > > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > > +                                         enum mtk_ddp_comp_id next,
> > > +                                         unsigned int *addr)
> > > +{
> > > +       unsigned int value;
> > > +
> > > +       if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> > > +               *addr = DISP_OVL0_2L_MOUT_EN;
> > > +               value = OVL0_MOUT_EN_DISP_RDMA0;
> > > +       } else if (cur == DDP_COMPONENT_OVL_2L2 && next == DDP_COMPONENT_RDMA4) {
> > > +               *addr = DISP_OVL2_2L_MOUT_EN;
> > > +               value = OVL2_2L_MOUT_RDMA4;
> > > +       } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> > > +               *addr = DISP_DITHER0_MOUT_EN;
> > > +               value = DITHER0_MOUT_DSI0;
> > > +       } else {
> > > +               value = 0;
> > > +       }
> > > +
> > > +       return value;
> > > +}
> > > +
> > > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > > +                                        enum mtk_ddp_comp_id next,
> > > +                                        unsigned int *addr)
> > > +{
> > > +       unsigned int value;
> > > +
> > > +       if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_RDMA0) {
> > > +               *addr = DISP_RDMA0_SEL_IN;
> > > +               value = RDMA0_SEL_IN_OVL0_2L;
> > > +       } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> > > +               *addr = DISP_AAL0_SEL_IN;
> > > +               value = AAL0_SEL_IN_CCORR0;
> > > +       } else if (cur == DDP_COMPONENT_DITHER && next == DDP_COMPONENT_DSI0) {
> > > +               *addr = DISP_DSI0_SEL_IN;
> > > +               value = DSI0_SEL_IN_DITHER0;
> > > +       } else {
> > > +               value = 0;
> > > +       }
> > > +
> > > +       return value;
> > > +}
> > > +
> > > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> > > +                                  enum mtk_ddp_comp_id cur,
> > > +                                  enum mtk_ddp_comp_id next)
> > > +{
> > > +       if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) {
> > > +               writel_relaxed(RDMA0_SOUT_COLOR0, config_regs + DISP_RDMA0_SOUT_SEL);
> > > +       } else if (cur == DDP_COMPONENT_CCORR && next == DDP_COMPONENT_AAL0) {
> > > +               writel_relaxed(CCORR0_SOUT_AAL0, config_regs + DISP_CCORR0_SOUT_SEL);
> > > +       }
> > > +}
> > > +
> > > +static unsigned int mtk_mmsys_ovl_mout_en(enum mtk_ddp_comp_id cur,
> > > +                                         enum mtk_ddp_comp_id next,
> > > +                                         unsigned int *addr)
> > > +{
> > > +       int value = -1;
> > > +
> > > +       *addr = MMSYS_OVL_MOUT_EN;
> > > +
> > > +       if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL_2L0)
> > > +               value = DISP_OVL0_GO_BG;
> > > +       else if (cur == DDP_COMPONENT_OVL_2L0 && next == DDP_COMPONENT_OVL0)
> > > +               value = DISP_OVL0_2L_GO_BG;
> > > +       else if (cur == DDP_COMPONENT_OVL0)
> > > +               value = DISP_OVL0_GO_BLEND;
> > > +       else if (cur == DDP_COMPONENT_OVL_2L0)
> > > +               value = DISP_OVL0_2L_GO_BLEND;
> > > +       else
> > > +               value = -1;
> > > +
> > > +       return value;
> > > +}
> >
> > I think you should squash mtk_mmsys_ovl_mout_en() with mtk_mmsys_ddp_mout_en().
> >
> > Regards,
> > Chun-Kuang.
>
> hi
>
> in soc mt8192,  ovl0_2l -> rdma0 usecase need set 2 register:
> DISP_OVL0_2L_MOUT_EN and MMSYS_OVL_MOUT_EN,
> 'if-else' in mtk_mmsys_ddp_mout_en can not cover this case.
>

I think mtk_mmsys_ddp_mout_en() could work as mtk_mmsys_ddp_mout_en().
This mean that mtk_mmsys_ddp_mout_en() could write register inside it
rather than return value and write register in
mtk_mmsys_ddp_connect().

Regards,
Chun-Kuang.

> >
> > > +
> > > +struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs = {
> > > +       .mout_en = mtk_mmsys_ddp_mout_en,
> > > +       .ovl_mout_en = mtk_mmsys_ovl_mout_en,
> > > +       .sel_in = mtk_mmsys_ddp_sel_in,
> > > +       .sout_sel = mtk_mmsys_ddp_sout_sel,
> > > +};
> > > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > > index 220203d..efa07b9 100644
> > > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > > @@ -62,6 +62,7 @@ struct mtk_mmsys_conn_funcs {
> > >
> > >  extern struct mtk_mmsys_conn_funcs mt2701_mmsys_funcs;
> > >  extern struct mtk_mmsys_conn_funcs mt8183_mmsys_funcs;
> > > +extern struct mtk_mmsys_conn_funcs mt8192_mmsys_funcs;
> > >
> > >  void mtk_mmsys_ddp_connect(struct device *dev,
> > >                            enum mtk_ddp_comp_id cur,
> > > --
> > > 1.8.1.1.dirty
> > > _______________________________________________
> > > Linux-mediatek mailing list
> > > Linux-mediatek@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-mediatek
>

Re: [PATCH v2, 01/17] dt-bindings: mediatek: add description for postmask

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:12寫道：
>
> add description for postmask

What is postmask? I google it and find a postmask ECO. So it is postmask ECO?

Regards,
Chun-Kuang.

>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index 5ca693a..1972fa7 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -37,6 +37,7 @@ Required properties (all function blocks):
>         "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
>         "mediatek,<chip>-disp-gamma"            - gamma correction
>         "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> +       "mediatek,<chip>-disp-postmask"         - post mask
>         "mediatek,<chip>-disp-split"            - split stream to two encoders
>         "mediatek,<chip>-disp-ufoe"             - data compression engine
>         "mediatek,<chip>-dsi"                   - DSI controller, see mediatek,dsi.txt
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 01/17] dt-bindings: mediatek: add description for postmask

[Rob Herring]

On Sat, Dec 12, 2020 at 12:11:41PM +0800, Yongqiang Niu wrote:
> add description for postmask
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index 5ca693a..1972fa7 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -37,6 +37,7 @@ Required properties (all function blocks):
>  	"mediatek,<chip>-disp-aal"   		- adaptive ambient light controller
>  	"mediatek,<chip>-disp-gamma" 		- gamma correction
>  	"mediatek,<chip>-disp-merge" 		- merge streams from two RDMA sources
> +	"mediatek,<chip>-disp-postmask" 	- post mask

Needs a better explanation. What's the type? Constraints on the values?

>  	"mediatek,<chip>-disp-split" 		- split stream to two encoders
>  	"mediatek,<chip>-disp-ufoe"  		- data compression engine
>  	"mediatek,<chip>-dsi"        		- DSI controller, see mediatek,dsi.txt
> -- 
> 1.8.1.1.dirty
> 

Re: [PATCH v2, 03/17] dt-bindings: mediatek: add description for mt8192 display

[Rob Herring]

On Sat, 12 Dec 2020 12:11:43 +0800, Yongqiang Niu wrote:
> add description for mt8192 display
> 
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2, 10/17] drm/mediatek: fix aal size config

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:22寫道：
>
> fix aal size config
>
> Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index be61d11..e7d481e0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -33,8 +33,13 @@
>  #define DISP_REG_UFO_START                     0x0000
>
>  #define DISP_AAL_EN                            0x0000
> +#define DISP_AAL_CFG                           0x0020
> +#define AAL_RELAY_MODE                                 BIT(0)
> +#define AAL_ENGINE_EN                                  BIT(1)
>  #define DISP_AAL_SIZE                          0x0030
>
> +#define DISP_AAL_OUTPUT_SIZE                   0x04d8
> +
>  #define DISP_CCORR_EN                          0x0000
>  #define CCORR_EN                               BIT(0)
>  #define DISP_CCORR_CFG                         0x0020
> @@ -184,7 +189,11 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
>                            unsigned int h, unsigned int vrefresh,
>                            unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
>  {
> -       mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
> +       mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_OUTPUT_SIZE);
> +
> +       mtk_ddp_write_mask(NULL, AAL_RELAY_MODE, comp, DISP_AAL_CFG,

cmdq_pkt

> +                          AAL_RELAY_MODE | AAL_ENGINE_EN);

This patch is to fix size config, so move this statement to another patch.

Regards,
Chun-Kuang.

>  }
>
>  static void mtk_aal_start(struct mtk_ddp_comp *comp)
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 02/17] dt-bindings: mediatek: add CLK_MM_DISP_CONFIG control description for mt8192 display

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:12寫道：
>
> add CLK_MM_DISP_CONFIG control description for mt8192 displa

display

>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
>  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index 1972fa7..dfbec76 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -54,6 +54,9 @@ Required properties (all function blocks):
>    DPI controller nodes have multiple clock inputs. These are documented in
>    mediatek,dsi.txt and mediatek,dpi.txt, respectively.
>    An exception is that the mt8183 mutex is always free running with no clocks property.
> +  An exception is that the mt8192 display add 2 more clocks(CLK_MM_DISP_CONFIG, CLK_MM_26MHZ),
> +  and these 2 clocks need enabled before display module work like mutex clock, so we add these
> +  2 clocks controled same with mutex clock.

If every display module needs these two clock, add these two clock to
all the display module which need them.

Regards,
Chun-Kuang.

>
>  Required properties (DMA function blocks):
>  - compatible: Should be one of
> --
> 1.8.1.1.dirty
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 01/17] dt-bindings: mediatek: add description for postmask

[Yongqiang Niu]

On Tue, 2020-12-15 at 22:49 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:12寫道：
> >
> > add description for postmask
> 
> What is postmask? I google it and find a postmask ECO. So it is postmask ECO?
> 
> Regards,
> Chun-Kuang.
> 

it is used control round corner for display frame

> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > index 5ca693a..1972fa7 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > @@ -37,6 +37,7 @@ Required properties (all function blocks):
> >         "mediatek,<chip>-disp-aal"              - adaptive ambient light controller
> >         "mediatek,<chip>-disp-gamma"            - gamma correction
> >         "mediatek,<chip>-disp-merge"            - merge streams from two RDMA sources
> > +       "mediatek,<chip>-disp-postmask"         - post mask
> >         "mediatek,<chip>-disp-split"            - split stream to two encoders
> >         "mediatek,<chip>-disp-ufoe"             - data compression engine
> >         "mediatek,<chip>-dsi"                   - DSI controller, see mediatek,dsi.txt
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 02/17] dt-bindings: mediatek: add CLK_MM_DISP_CONFIG control description for mt8192 display

[Yongqiang Niu]

On Wed, 2020-12-16 at 23:17 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:12寫道：
> >
> > add CLK_MM_DISP_CONFIG control description for mt8192 displa
> 
> display
> 
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > index 1972fa7..dfbec76 100644
> > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> > @@ -54,6 +54,9 @@ Required properties (all function blocks):
> >    DPI controller nodes have multiple clock inputs. These are documented in
> >    mediatek,dsi.txt and mediatek,dpi.txt, respectively.
> >    An exception is that the mt8183 mutex is always free running with no clocks property.
> > +  An exception is that the mt8192 display add 2 more clocks(CLK_MM_DISP_CONFIG, CLK_MM_26MHZ),
> > +  and these 2 clocks need enabled before display module work like mutex clock, so we add these
> > +  2 clocks controled same with mutex clock.
> 
> If every display module needs these two clock, add these two clock to
> all the display module which need them.
> 
> Regards,
> Chun-Kuang.

all display module work need mutex clock work on, but not add mutex
clock into all display module
> 
> >
> >  Required properties (DMA function blocks):
> >  - compatible: Should be one of
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 04/17] drm/mediatek: add component OVL_2L2

[Yongqiang Niu]

On Sun, 2020-12-13 at 09:15 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:12寫道：
> >
> > This patch add component OVL_2L2
> 
> Break drm part and soc part into different patches.
> 
> Regards,
> Chun-Kuang.

will be fixed in next version
> 
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
> >  include/linux/soc/mediatek/mtk-mmsys.h      | 1 +
> >  2 files changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 8eba44b..8938554 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -403,6 +403,7 @@ struct mtk_ddp_comp_match {
> >         [DDP_COMPONENT_OVL1]    = { MTK_DISP_OVL,       1, NULL },
> >         [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L,    0, NULL },
> >         [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L,    1, NULL },
> > +       [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L,    2, NULL },
> >         [DDP_COMPONENT_PWM0]    = { MTK_DISP_PWM,       0, NULL },
> >         [DDP_COMPONENT_PWM1]    = { MTK_DISP_PWM,       1, NULL },
> >         [DDP_COMPONENT_PWM2]    = { MTK_DISP_PWM,       2, NULL },
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 4b6c514..42476c2 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -29,6 +29,7 @@ enum mtk_ddp_comp_id {
> >         DDP_COMPONENT_OVL0,
> >         DDP_COMPONENT_OVL_2L0,
> >         DDP_COMPONENT_OVL_2L1,
> > +       DDP_COMPONENT_OVL_2L2,
> >         DDP_COMPONENT_OVL1,
> >         DDP_COMPONENT_PWM0,
> >         DDP_COMPONENT_PWM1,
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 07/17] drm/mediatek: add disp config and mm 26mhz clock into mutex device

[Yongqiang Niu]

On Tue, 2020-12-15 at 21:37 +0800, Nicolas Boichat wrote:
> On Sat, Dec 12, 2020 at 12:12 PM Yongqiang Niu
> <yongqiang.niu@mediatek.com> wrote:
> >
> > there are 2 more clock need enable for display.
> > parser these clock when mutex device probe,
> > enable and disable when mutex on/off
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 49 ++++++++++++++++++++++++++++------
> >  1 file changed, 41 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index 60788c1..de618a1 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -118,7 +118,7 @@ struct mtk_ddp_data {
> >
> >  struct mtk_ddp {
> >         struct device                   *dev;
> > -       struct clk                      *clk;
> > +       struct clk                      *clk[3];
> >         void __iomem                    *regs;
> >         struct mtk_disp_mutex           mutex[10];
> >         const struct mtk_ddp_data       *data;
> > @@ -257,14 +257,39 @@ int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex)
> >  {
> >         struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> >                                            mutex[mutex->id]);
> > -       return clk_prepare_enable(ddp->clk);
> > +       int ret;
> > +       int i;
> > +
> > +       for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
> > +               if (IS_ERR(ddp->clk[i]))
> > +                       continue;
> > +               ret = clk_prepare_enable(ddp->clk[i]);
> > +               if (ret) {
> > +                       pr_err("failed to enable clock, err %d. i:%d\n",
> > +                               ret, i);
> > +                       goto err;
> > +               }
> > +       }
> > +
> > +       return 0;
> > +
> > +err:
> > +       while (--i >= 0)
> > +               clk_disable_unprepare(ddp->clk[i]);
> > +       return ret;
> >  }
> >
> >  void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex)
> >  {
> >         struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> >                                            mutex[mutex->id]);
> > -       clk_disable_unprepare(ddp->clk);
> > +       int i;
> > +
> > +        for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
> > +               if (IS_ERR(ddp->clk[i]))
> > +                       continue;
> > +               clk_disable_unprepare(ddp->clk[i]);
> > +       }
> >  }
> >
> >  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> > @@ -415,11 +440,19 @@ static int mtk_ddp_probe(struct platform_device *pdev)
> >         ddp->data = of_device_get_match_data(dev);
> >
> >         if (!ddp->data->no_clk) {
> > -               ddp->clk = devm_clk_get(dev, NULL);
> > -               if (IS_ERR(ddp->clk)) {
> > -                       if (PTR_ERR(ddp->clk) != -EPROBE_DEFER)
> > -                               dev_err(dev, "Failed to get clock\n");
> > -                       return PTR_ERR(ddp->clk);
> > +               int ret;
> > +
> > +               for (i = 0; i < ARRAY_SIZE(ddp->clk); i++) {
> > +                       ddp->clk[i] = of_clk_get(dev->of_node, i);
> > +
> > +                       if (IS_ERR(ddp->clk[i])) {
> > +                               ret = PTR_ERR(ddp->clk[i]);
> > +                               if (ret != EPROBE_DEFER)
> > +                                       dev_err(dev, "Failed to get clock %d\n",
> > +                                               ret);
> > +
> > +                               return ret;
> > +                       }
> 
> Use of_clk_bulk_get_all instead?
> 
> ddp->num_clks = of_clk_bulk_get_all(dev->of_node, &ddp->clks);
> ...
> 
> Then the calls above can be clk_bulk_enable/clk_bulk_disable using
> num_clks and clks.
> 

will be fixed in next version
> 
> >                 }
> >         }
> >
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 10/17] drm/mediatek: fix aal size config

[Yongqiang Niu]

On Wed, 2020-12-16 at 23:10 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:22寫道：
> >
> > fix aal size config
> >
> > Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index be61d11..e7d481e0 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -33,8 +33,13 @@
> >  #define DISP_REG_UFO_START                     0x0000
> >
> >  #define DISP_AAL_EN                            0x0000
> > +#define DISP_AAL_CFG                           0x0020
> > +#define AAL_RELAY_MODE                                 BIT(0)
> > +#define AAL_ENGINE_EN                                  BIT(1)
> >  #define DISP_AAL_SIZE                          0x0030
> >
> > +#define DISP_AAL_OUTPUT_SIZE                   0x04d8
> > +
> >  #define DISP_CCORR_EN                          0x0000
> >  #define CCORR_EN                               BIT(0)
> >  #define DISP_CCORR_CFG                         0x0020
> > @@ -184,7 +189,11 @@ static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
> >                            unsigned int h, unsigned int vrefresh,
> >                            unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> >  {
> > -       mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_AAL_OUTPUT_SIZE);
> > +
> > +       mtk_ddp_write_mask(NULL, AAL_RELAY_MODE, comp, DISP_AAL_CFG,
> 
> cmdq_pkt
> 
> > +                          AAL_RELAY_MODE | AAL_ENGINE_EN);
> 
> This patch is to fix size config, so move this statement to another patch.
> 
> Regards,
> Chun-Kuang.
> 

will be fixed in next version

> >  }
> >
> >  static void mtk_aal_start(struct mtk_ddp_comp *comp)
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 12/17] drm/mediatek: fix gamma size config

[Yongqiang Niu]

On Tue, 2020-12-15 at 07:40 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
> 
> Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:13寫道：
> >
> > fix gamma size config
> 
> I would like you to provide more information. The original code works
> in mt8173, why do you modify this? The description may be something
> like this:
> 
> According to data sheet, the width is in bits [31, 16] and height is
> in bits [15, 0]. Even though wrong setting may works in some SoC such
> as mt8173, but it does not work in mt8192.
> 
> Regards,
> Chun-Kuang.

it still works in mt8192.
just modify this follow data sheet

> 
> >
> > Fixes: e0a5d3370245 (drm/mediatek: Add GAMMA engine basic function)
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 00d5687..52b6fc7 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -297,7 +297,7 @@ static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
> >                              unsigned int h, unsigned int vrefresh,
> >                              unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> >  {
> > -       mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
> > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_GAMMA_SIZE);
> >         mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
> >  }
> >
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 14/17] soc: mediatek: mmsys: Use function call for setting mmsys ovl mout register

[Yongqiang Niu]

On Tue, 2020-12-15 at 21:42 +0800, Nicolas Boichat wrote:
> On Sat, Dec 12, 2020 at 12:13 PM Yongqiang Niu
> <yongqiang.niu@mediatek.com> wrote:
> >
> > Use function call for setting mmsys ovl mout register
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > ---
> >  drivers/soc/mediatek/mmsys/mtk-mmsys.c | 18 ++++++++++++++++++
> >  include/linux/soc/mediatek/mtk-mmsys.h |  3 +++
> >  2 files changed, 21 insertions(+)
> >
> > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > index cb76e64..2558b42 100644
> > --- a/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c
> > @@ -78,6 +78,15 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> >                 reg = readl_relaxed(mmsys->regs + addr) | value;
> >                 writel_relaxed(reg, mmsys->regs + addr);
> >         }
> > +
> > +       if (!funcs->ovl_mout_en)
> > +               return;
> > +
> > +       value = funcs->ovl_mout_en(cur, next, &addr);
> > +       if (value) {
> > +               reg = readl_relaxed(mmsys->regs + addr) | value;
> > +               writel_relaxed(reg, mmsys->regs + addr);
> > +       }
> 
> This is technically correct, but I'm afraid this may become and issue
> later if we have another function like ovl_mout_en.
> 
> So maybe it's better to do:
> if (funcs->ovl_mout_en) {
>   value = funcs->ovl_mout_en(cur, next, &addr);
>   ...
> }

will be improved like this in next version
> 
> Or another option: Create a new function
> static unsigned int mtk_mmsys_ovl_mout_en(...) {
>    if (!funcs->ovl_mout_en)
>       return 0;
> }
> 
> and call that, following the same pattern as
> mtk_mmsys_ddp_mout_en/mtk_mmsys_ddp_sel_in?
> 
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
> >
> > @@ -103,6 +112,15 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> >                 reg = readl_relaxed(mmsys->regs + addr) & ~value;
> >                 writel_relaxed(reg, mmsys->regs + addr);
> >         }
> > +
> > +       if (!funcs->ovl_mout_en)
> > +               return;
> > +
> > +       value = funcs->ovl_mout_en(cur, next, &addr);
> > +       if (value) {
> > +               reg = readl_relaxed(mmsys->regs + addr) & ~value;
> > +               writel_relaxed(reg, mmsys->regs + addr);
> > +       }
> >  }
> >  EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > index aa4f60e..220203d 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -49,6 +49,9 @@ struct mtk_mmsys_conn_funcs {
> >         u32 (*mout_en)(enum mtk_ddp_comp_id cur,
> >                        enum mtk_ddp_comp_id next,
> >                        unsigned int *addr);
> > +       u32 (*ovl_mout_en)(enum mtk_ddp_comp_id cur,
> > +                          enum mtk_ddp_comp_id next,
> > +                          unsigned int *addr);
> >         u32 (*sel_in)(enum mtk_ddp_comp_id cur,
> >                       enum mtk_ddp_comp_id next,
> >                       unsigned int *addr);
> > --
> > 1.8.1.1.dirty
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH v2, 12/17] drm/mediatek: fix gamma size config

[Chun-Kuang Hu]

Hi, Yongqiang:

Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月23日 週三 上午9:37寫道：
>
> On Tue, 2020-12-15 at 07:40 +0800, Chun-Kuang Hu wrote:
> > Hi, Yongqiang:
> >
> > Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2020年12月12日 週六 下午12:13寫道：
> > >
> > > fix gamma size config
> >
> > I would like you to provide more information. The original code works
> > in mt8173, why do you modify this? The description may be something
> > like this:
> >
> > According to data sheet, the width is in bits [31, 16] and height is
> > in bits [15, 0]. Even though wrong setting may works in some SoC such
> > as mt8173, but it does not work in mt8192.
> >
> > Regards,
> > Chun-Kuang.
>
> it still works in mt8192.
> just modify this follow data sheet

This patch is not strongly related to MT8192, so move this patch out
of this series.

Regards,
Chun-Kuang.

>
> >
> > >
> > > Fixes: e0a5d3370245 (drm/mediatek: Add GAMMA engine basic function)
> > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > > ---
> > >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > index 00d5687..52b6fc7 100644
> > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > > @@ -297,7 +297,7 @@ static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
> > >                              unsigned int h, unsigned int vrefresh,
> > >                              unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > >  {
> > > -       mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
> > > +       mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_GAMMA_SIZE);
> > >         mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
> > >  }
> > >
> > > --
> > > 1.8.1.1.dirty
> > > _______________________________________________
> > > Linux-mediatek mailing list
> > > Linux-mediatek@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-mediatek
>