From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40B7CC433F5 for ; Sun, 5 Sep 2021 04:11:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 257E860232 for ; Sun, 5 Sep 2021 04:11:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232665AbhIEEMX (ORCPT ); Sun, 5 Sep 2021 00:12:23 -0400 Received: from mail.kernel.org ([198.145.29.99]:32952 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229541AbhIEEMW (ORCPT ); Sun, 5 Sep 2021 00:12:22 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id A9CF061057; Sun, 5 Sep 2021 04:11:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1630815079; bh=FJt08tLv94mGzxxoL9aKwkbFQx3aABVQCv3d6GkPJ50=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=BkGVJHzzLOWSqg7qiTcFvDwkAz7IvFkSPRqU6MLqjnzLUWEoRoJy2C04dJn99rBm2 8jPItABi5toutqoXFN7bM90fBVnhJctZFwug62V6r3xFeTscbRp0JvDH9H/A3LN+TT W1Gmfpo56UaDXGE87GY5qVU9754eKQXwsBguLTUYTDkTq2/pIgOa2Frcjx94/5JwHH 9a8KzjE3uUo790W8f4D/3x8jzlwDMQvYaar4a1HpaQQ6gzzyLlZdudj0/SfiokpXOl P7hUBdLNpNlY3VNCQ65Oe/ZsaSCUQGvr3dTsCkfHEB03sj3RhWEtR3Bo3svALVk8rp j18hxIAIQzSfg== Received: by mail-ej1-f44.google.com with SMTP id x11so6432366ejv.0; Sat, 04 Sep 2021 21:11:19 -0700 (PDT) X-Gm-Message-State: AOAM532jvlouIaRSi+f4tym1fc6Dxqtv/JBOlBtpUISHbW2Rv+hGsjry bBT/HXKXW5xYDiCDAcd33AWbgzeFmdjuLhHZFA== X-Google-Smtp-Source: ABdhPJxuQktwkT66NyxvIWF/PbhLjJE31qsp+wgNqVEER3VZSiT7tBa60/3ZxcrdU/9Low1/zRYZ7e6Rc2WPzONInhU= X-Received: by 2002:a17:906:26c4:: with SMTP id u4mr6927063ejc.511.1630815078141; Sat, 04 Sep 2021 21:11:18 -0700 (PDT) MIME-Version: 1.0 References: <20210825144833.7757-1-jason-jh.lin@mediatek.com> <20210825144833.7757-5-jason-jh.lin@mediatek.com> In-Reply-To: <20210825144833.7757-5-jason-jh.lin@mediatek.com> From: Chun-Kuang Hu Date: Sun, 5 Sep 2021 12:11:07 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v9 04/14] dt-bindings: mediatek: add mediatek,dsc.yaml for mt8195 SoC binding To: "jason-jh.lin" Cc: Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , Enric Balletbo i Serra , Frank Wunderlich , David Airlie , Daniel Vetter , Fabien Parent , Hsin-Yi Wang , fshao@chromium.org, Yongqiang Niu , Jitao shi , Nancy Lin , singo.chang@mediatek.com, DTML , Linux ARM , "moderated list:ARM/Mediatek SoC support" , linux-kernel , DRI Development Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Jason: jason-jh.lin =E6=96=BC 2021=E5=B9=B48=E6=9C=882= 5=E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=8810:48=E5=AF=AB=E9=81=93=EF= =BC=9A > > 1. Add mediatek,dsc.yaml to describe DSC module in details. > 2. Add mt8195 SoC binding to mediatek,dsc.yaml. > > Signed-off-by: jason-jh.lin > --- > .../display/mediatek/mediatek,dsc.yaml | 70 +++++++++++++++++++ > 1 file changed, 70 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/me= diatek,dsc.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,= dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.= yaml > new file mode 100644 > index 000000000000..f26e3010d5f4 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yam= l > @@ -0,0 +1,70 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: mediatek display DSC controller Mediatek Regards, Chun-Kuang. > + > +maintainers: > + - Chun-Kuang Hu > + - Philipp Zabel > + > +description: | > + The DSC standard is a specification of the algorithms used for > + compressing and decompressing image display streams, including > + the specification of the syntax and semantics of the compressed > + video bit stream. DSC is designed for real-time systems with > + real-time compression, transmission, decompression and Display. > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: mediatek,mt8195-disp-dsc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: DSC Wrapper Clock > + > + power-domains: > + description: A phandle and PM domain specifier as defined by binding= s of > + the power controller specified by phandle. See > + Documentation/devicetree/bindings/power/power-domain.yaml for deta= ils. > + > + > + mediatek,gce-client-reg: > + description: > + The register of client driver can be configured by gce with 4 argu= ments defined > + in this property, such as phandle of gce, subsys id, register offs= et and size. > + Each subsys id is mapping to a base address of display function bl= ocks register > + which is defined in the gce header include/include/dt-bindings/gce= /-gce.h. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + > + dsc0: disp_dsc_wrap@1c009000 { > + compatible =3D "mediatek,mt8195-disp-dsc"; > + reg =3D <0 0x1c009000 0 0x1000>; > + interrupts =3D ; > + power-domains =3D <&spm MT8195_POWER_DOMAIN_VDOSYS0>; > + clocks =3D <&vdosys0 CLK_VDO0_DSC_WRAP0>; > + mediatek,gce-client-reg =3D <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000= >; > + }; > -- > 2.18.0 >