From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 692D2C433F5 for ; Wed, 27 Oct 2021 23:47:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 4A74761073 for ; Wed, 27 Oct 2021 23:47:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229658AbhJ0XuW (ORCPT ); Wed, 27 Oct 2021 19:50:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:44330 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229447AbhJ0XuU (ORCPT ); Wed, 27 Oct 2021 19:50:20 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 3BF32610FD for ; Wed, 27 Oct 2021 23:47:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1635378473; bh=t+PpqypSCKapTKRguvjCBaJPzX1t0c7f7uN58dcUX7k=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=g35vda8IPAZHnszM/A969Xutm5EPOZJyoiXZ6xXU5xMhupCFrKeb2gAzsFABGAJO9 JZmzqgM1jCV7X2r00r3JANnowHEwoGcx6YT5cHvQuDiBliY1FnnIewjQ98rtxKvIyP 8H4po/ArJBCEdqHRTuKXeEitONH/RP+rIqsLx609a3SzptaiBKFwNKtM//ImcIi692 GNFPf//j06uYa4Z6s0uJH5Yd5j6cNsygjaYvJwMSBbzJxlGYVNoMWjMUllt75wFAjs WwWicaSlYeI9CXqZvPpftCo5DS+s6yS0xLl+EP20WZa+sXrwDgWXDGgAko1VPRsUmH o+tvCXbwDoHBw== Received: by mail-ed1-f43.google.com with SMTP id s1so17183256edd.3 for ; Wed, 27 Oct 2021 16:47:53 -0700 (PDT) X-Gm-Message-State: AOAM532N/5mwmnUxkX02OhkiIfxIwwIZkS6GY0ujGXbYe0UX78Lu1MiO nAIT3OBWpSFi/aR0A61e7ZnNimi2B1Pfk2I/5Q== X-Google-Smtp-Source: ABdhPJxg4eUZljI10gC+7+cwqF6vxnwg2Rr90TkBscgjdcWRIhtecmw9FjFNDtU5mtrkdv/lNBHMmDxTzmNvXUH9TzE= X-Received: by 2002:a05:6402:28f:: with SMTP id l15mr1357751edv.272.1635378471564; Wed, 27 Oct 2021 16:47:51 -0700 (PDT) MIME-Version: 1.0 References: <20211027021857.20816-1-jason-jh.lin@mediatek.com> <20211027021857.20816-4-jason-jh.lin@mediatek.com> In-Reply-To: From: Chun-Kuang Hu Date: Thu, 28 Oct 2021 07:47:40 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 3/6] drm/mediatek: Detect CMDQ execution timeout To: Fei Shao Cc: "jason-jh.lin" , Chun-Kuang Hu , Philipp Zabel , Matthias Brugger , Jassi Brar , Yongqiang Niu , David Airlie , Daniel Vetter , DRI Development , "moderated list:ARM/Mediatek SoC support" , Linux ARM , linux-kernel , Hsin-Yi Wang , Nancy Lin , singo.chang@mediatek.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Fei: Fei Shao =E6=96=BC 2021=E5=B9=B410=E6=9C=8827=E6=97=A5= =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=885:32=E5=AF=AB=E9=81=93=EF=BC=9A > > Hi Jason, > > On Wed, Oct 27, 2021 at 10:19 AM jason-jh.lin = wrote: > > > > From: Chun-Kuang Hu > > > > CMDQ is used to update display register in vblank period, so > > it should be execute in next 2 vblank. One vblank interrupt > > before send message (occasionally) and one vblank interrupt > > after cmdq done. If it fail to execute in next 3 vblank, > > tiemout happen. > > > > Signed-off-by: Chun-Kuang Hu > > Signed-off-by: jason-jh.lin > > Reviewed-by: Chun-Kuang Hu > > --- > > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 20 ++++++++++++++++++-- > > 1 file changed, 18 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/= mediatek/mtk_drm_crtc.c > > index e23e3224ac67..dad1f85ee315 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > > @@ -54,6 +54,7 @@ struct mtk_drm_crtc { > > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > > struct cmdq_client cmdq_client; > > u32 cmdq_event; > > + u32 cmdq_vblank_cnt; > > #endif > > > > struct device *mmsys_dev; > > @@ -227,7 +228,10 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(st= ruct drm_crtc *crtc, > > static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) > > { > > struct cmdq_cb_data *data =3D mssg; > > + struct cmdq_client *cmdq_cl =3D container_of(cl, struct cmdq_cl= ient, client); > > + struct mtk_drm_crtc *mtk_crtc =3D container_of(cmdq_cl, struct = mtk_drm_crtc, cmdq_client); > > > > + mtk_crtc->cmdq_vblank_cnt =3D 0; > > cmdq_pkt_destroy(data->pkt); > > } > > #endif > > @@ -483,6 +487,15 @@ static void mtk_drm_crtc_update_config(struct mtk_= drm_crtc *mtk_crtc, > > cmdq_handle->pa_base, > > cmdq_handle->cmd_buf_size, > > DMA_TO_DEVICE); > > + /* > > + * CMDQ command should execute in next 3 vblank. > > + * One vblank interrupt before send message (occasional= ly) > > + * and one vblank interrupt after cmdq done, > > + * so it's timeout after 3 vblank interrupt. > > + * If it fail to execute in next 3 vblank, timeout happ= en. > > + */ > > + mtk_crtc->cmdq_vblank_cnt =3D 3; > > + > > mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_hand= le); > > mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0); > > } > > @@ -499,11 +512,14 @@ static void mtk_crtc_ddp_irq(void *data) > > > > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > > if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan= ) > > + mtk_crtc_ddp_config(crtc, NULL); > > + else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vbla= nk_cnt =3D=3D 0) > I think atomic_dec_and_test() does what you want to do here. I think this operation is not necessary to be atomic operation, and this statement could be reduced to else if (--mtk_crtc->cmdq_vblank_cnt =3D=3D 0) > > > > > > + DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n"= , > > + drm_crtc_index(&mtk_crtc->base)); > > #else > > if (!priv->data->shadow_register) > > -#endif > > mtk_crtc_ddp_config(crtc, NULL); > > - > > +#endif > > mtk_drm_finish_page_flip(mtk_crtc); > > } > > > > -- > > 2.18.0 > >