From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDA3BC432BE for ; Thu, 26 Aug 2021 00:33:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 92A21610A7 for ; Thu, 26 Aug 2021 00:33:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235182AbhHZAeC (ORCPT ); Wed, 25 Aug 2021 20:34:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:52838 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231210AbhHZAeB (ORCPT ); Wed, 25 Aug 2021 20:34:01 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 128C1610A7 for ; Thu, 26 Aug 2021 00:33:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1629937995; bh=SbycQ9kZqssax3PP+kHq0IDJta79FNerEMDO87wY3QM=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=n9GhZ42ev+K3L8aZKa5NSttM7oT98wtFhKL2i5OgqQy7x2QJADHrUhgisvMKEb8Da 006maSkL7oNvIaxWdePEmBp37JAZ/RUTm+d2r++UGsCe1lg1V0DFUCU/T5VM9tH5Yt Uy3l13oK2R1CmSmOWUF8KZ2/9INRPgvyug8zTaWkn5FaytsG/854/A0ub6wzs+RXto Oa4VFBwJVlABrDUvn2gyhKl/L95HSttYDW8gQTm/VX4YQGrO3e93zyJ/9uzc2FDhuq VCEAHbZomI+c0xNM3ied2ceWgM5qs7HULhNYG9DAaI+4xinD27aB6EYoLRnqIKuORN uYzEqBcDmFwmw== Received: by mail-ed1-f52.google.com with SMTP id i6so1848498edu.1 for ; Wed, 25 Aug 2021 17:33:14 -0700 (PDT) X-Gm-Message-State: AOAM533BTrwmiznSWpWzIyKhpku0omuoFC/7bI9Nhw1N1iPeWgjjxwfI JKomlCgjdRtyYMUC2qVMDcRu8NRHC2qnLhk8MQ== X-Google-Smtp-Source: ABdhPJyBPuQaGp8lfnXeBg0U5q3Cqp6INUxGUp0eCq4GNnGDtFawyemhfYjZTPeZHt4IH5oA9wNJxuhramUAwgIbgtc= X-Received: by 2002:aa7:d351:: with SMTP id m17mr1303182edr.72.1629937993715; Wed, 25 Aug 2021 17:33:13 -0700 (PDT) MIME-Version: 1.0 References: <20210825102632.601614-1-enric.balletbo@collabora.com> <20210825122613.v3.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid> In-Reply-To: From: Chun-Kuang Hu Date: Thu, 26 Aug 2021 08:33:02 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 6/7] soc: mediatek: mmsys: Add reset controller support To: Philipp Zabel Cc: Enric Balletbo i Serra , linux-kernel , "Nancy.Lin" , Matthias Brugger , Hsin-Yi Wang , "moderated list:ARM/Mediatek SoC support" , Jitao Shi , Eizan Miyamoto , Nicolas Boichat , Chun-Kuang Hu , Collabora Kernel ML , Linux ARM Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Philipp Zabel =E6=96=BC 2021=E5=B9=B48=E6=9C=8825= =E6=97=A5 =E9=80=B1=E4=B8=89 =E4=B8=8B=E5=8D=886:46=E5=AF=AB=E9=81=93=EF=BC= =9A > > On Wed, 2021-08-25 at 12:26 +0200, Enric Balletbo i Serra wrote: > > Among other features the mmsys driver should implement a reset > > controller to be able to reset different bits from their space. > > > > Cc: Jitao Shi > > Suggested-by: Chun-Kuang Hu > > Signed-off-by: Enric Balletbo i Serra > > Reviewed-by: Philipp Zabel > > --- > > > > (no changes since v1) > > > > drivers/soc/mediatek/mtk-mmsys.c | 69 ++++++++++++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-mmsys.h | 2 + > > Cc: Nancy - this patch clashes with [1], please coordinate. > > [1] https://lore.kernel.org/linux-arm-kernel/20210825100531.5653-11-nancy= .lin@mediatek.com/ Enric's series is all reviewed or acked, so I think Nancy's series should base on Enric's series. Regards, Chun-Kuang. > > regards > Philipp