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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	"open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
	"open list:BROADCOM NVRAM DRIVER" <linux-mips@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>,
	stable@vger.kernel.org
Subject: Re: [PATCH v2 2/2] MIPS: Malta: Do not byte-swap accesses to the CBUS UART
Date: Sat, 26 Jun 2021 18:44:27 +0200	[thread overview]
Message-ID: <CAAdtpL6m6zRG7ruYdsjPjbuzuT64ZiBK9tuwcUGEcgkgTfFEmA@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2106260524430.37803@angie.orcam.me.uk>

On Sat, Jun 26, 2021 at 6:11 AM Maciej W. Rozycki <macro@orcam.me.uk> wrote:
>
> Correct big-endian accesses to the CBUS UART, a Malta on-board discrete
> TI16C550C part wired directly to the system controller's device bus, and
> do not use byte swapping with the 32-bit accesses to the device.
>
> The CBUS is used for devices such as the boot flash memory needed early
> on in system bootstrap even before PCI has been initialised.  Therefore
> it uses the system controller's device bus, which follows the endianness
> set with the CPU, which means no byte-swapping is ever required for data
> accesses to CBUS, unlike with PCI.
>
> The CBUS UART uses the UPIO_MEM32 access method, that is the `readl' and
> `writel' MMIO accessors, which on the MIPS platform imply byte-swapping
> with PCI systems.  Consequently the wrong byte lane is accessed with the
> big-endian configuration and the UART is not correctly accessed.
>
> As it happens the UPIO_MEM32BE access method makes use of the `ioread32'
> and `iowrite32' MMIO accessors, which still use `readl' and `writel'
> respectively, however they byte-swap data passed, effectively cancelling
> swapping done with the accessors themselves and making it suitable for
> the CBUS UART.
>
> Make the CBUS UART switch between UPIO_MEM32 and UPIO_MEM32BE then,
> based on the endianness selected.  With this change in place the device
> is correctly recognised with big-endian Malta at boot, along with the
> Super I/O devices behind PCI:
>
> Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
> printk: console [ttyS0] disabled
> serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
> printk: console [ttyS0] enabled
> printk: bootconsole [uart8250] disabled
> serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A
> serial8250.0: ttyS2 at MMIO 0x1f000900 (irq = 20, base_baud = 230400) is a 16550A
>
> Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
> Fixes: e7c4782f92fc ("[MIPS] Put an end to <asm/serial.h>'s long and annyoing existence")
> Cc: stable@vger.kernel.org # v2.6.23+
> ---
> Changes from v1:
>
> - Remove console message duplicates from the commit description.
> ---
>  arch/mips/mti-malta/malta-platform.c |    3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

      reply	other threads:[~2021-06-26 16:44 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-26  4:10 [PATCH v2 0/2] serial, Malta: Fixes to make the CBUS UART work big-endian Maciej W. Rozycki
2021-06-26  4:11 ` [PATCH v2 1/2] serial: 8250: Mask out floating 16/32-bit bus bits Maciej W. Rozycki
2021-06-26 16:42   ` Philippe Mathieu-Daudé
2021-06-26  4:11 ` [PATCH v2 2/2] MIPS: Malta: Do not byte-swap accesses to the CBUS UART Maciej W. Rozycki
2021-06-26 16:44   ` Philippe Mathieu-Daudé [this message]

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