From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2F3D0C433EF for ; Wed, 8 Sep 2021 08:35:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 06D2D61178 for ; Wed, 8 Sep 2021 08:35:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348230AbhIHIgr (ORCPT ); Wed, 8 Sep 2021 04:36:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348356AbhIHIgk (ORCPT ); Wed, 8 Sep 2021 04:36:40 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 23A63C061796 for ; Wed, 8 Sep 2021 01:35:31 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id q26so1998175wrc.7 for ; Wed, 08 Sep 2021 01:35:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=q+gTvqPkBS/9NQBkBlzTyY1pPZIuXVfqF0gdAjXvmEQ=; b=wDveK5lAB6l1NMxSINMMJExaTElhC1Hadv0ygYAfqTxaaYMv3IySUTUjp8bzuOPdRa bMndFJRdmVlulEHWcXp/LnteEs6vsNeOY8CT4htoyWxrJ74sTlvSEcRcZYgqmPILmOgc A4YtqmDEVblPPqigSHeeg7ICEqSpsHoL+p3C+kiue48QmlrgGL7sE0GJBJTwLjbOXfPl zJv9eJtsccvxTHkrB0VgN6p+n3N0t44AZxg77NZHqqyxv0+iSx2wngp0tllluH8IfgqJ G3WtqLaUK9i4s9Jzl6JIqkwOmtk7byhNg775DAh2t0Kjhwx/p35yVj+EesJNoCQpB2Rw NnoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=q+gTvqPkBS/9NQBkBlzTyY1pPZIuXVfqF0gdAjXvmEQ=; b=0cj9erxVya2JOmpEOrx2lKO3ljNW3mmSm/xELkpK28aksQUKtRy0w3mnopFaKwCGbX RrlwZ0zVu++bLd0paKbqjfbJblIQO9hkKCioAJO64ZCeIj/w4xO84SqnTFZ/QTdULYj5 tjy7B00nWkQUCHVNOOgL+DbNzlJEoJhmWeT+3nogbtAdSWkJ4f7y9YkZObzHAA47bocf UVyU33xAEb6K3+VrZ7bn5oIaDvKSiEElr34wA4WBO7361h6y58uXncjfgp8XvZ2z2QFy B5U8679SXWrb4Sq8nkUm6upqx96v6mLyZah0H82j4JNlcwq9+0zpFJcNgKZV/I2pTV7C BUFA== X-Gm-Message-State: AOAM532/183dlMtbOGkE5ywZdXJZJRPzmTUPTjm9ikUJcEehB+nhpWxX 2bVPHX1rXZyDeSo8dcNxCeMYL2OIx5LATutMT1hDvQ== X-Google-Smtp-Source: ABdhPJxnmqEbAAXw4ZZscbrlTqRG8a/a1xTdLDZhNeb4FqiNF0dwRr/GBN9JwQCWTsqYDoM7El3dNiZ090+mHhCE49A= X-Received: by 2002:adf:d1a8:: with SMTP id w8mr2667202wrc.306.1631090129589; Wed, 08 Sep 2021 01:35:29 -0700 (PDT) MIME-Version: 1.0 References: <20210907200254.467375-1-vgupta@kernel.org> In-Reply-To: <20210907200254.467375-1-vgupta@kernel.org> From: Anup Patel Date: Wed, 8 Sep 2021 14:05:18 +0530 Message-ID: Subject: Re: [PATCH] riscv: mm: don't advertise 1 num_asid for 0 asid bits To: Vineet Gupta Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Anup Patel , Jisheng Zhang , Guo Ren , Kefeng Wang , linux-riscv , "linux-kernel@vger.kernel.org List" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Sep 8, 2021 at 1:33 AM Vineet Gupta wrote: > > Even if mmu doesn't support ASID, current code calculates @num_asids=1 > which is misleading, so avoid setting any asid related variables in such > a case. > > Also while here, print the number of asid bits discovered even for the > disabled case. > > Verified this on Hifive Unmatched. > > Signed-off-by: Vineet Gupta > --- > arch/riscv/mm/context.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c > index ee3459cb6750..c8c6f8831a3b 100644 > --- a/arch/riscv/mm/context.c > +++ b/arch/riscv/mm/context.c > @@ -233,8 +233,10 @@ static int __init asids_init(void) > local_flush_tlb_all(); > > /* Pre-compute ASID details */ > - num_asids = 1 << asid_bits; > - asid_mask = num_asids - 1; > + if (asid_bits) { > + num_asids = 1 << asid_bits; > + asid_mask = num_asids - 1; > + } > > /* > * Use ASID allocator only if number of HW ASIDs are > @@ -255,7 +257,7 @@ static int __init asids_init(void) > pr_info("ASID allocator using %lu bits (%lu entries)\n", > asid_bits, num_asids); > } else { > - pr_info("ASID allocator disabled\n"); > + pr_info("ASID allocator disabled: %lu bits\n", asid_bits); May be use: pr_info("ASID allocator disabled (%lu bits)\n", asid_bits); for consistency with the ASID enabled case. Otherwise, it looks good to me. Reviewed-by: Anup Patel > } > > return 0; > -- > 2.30.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Regards, Anup