From: Anup Patel <anup@brainfault.org>
To: "Heiko Stübner" <heiko@sntech.de>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
"Rafael J . Wysocki" <rjw@rjwysocki.net>,
Pavel Machek <pavel@ucw.cz>, Rob Herring <robh+dt@kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Sandeep Tripathy <milun.tripathy@gmail.com>,
Atish Patra <atish.patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Liush <liush@allwinnertech.com>,
DTML <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
"open list:THERMAL" <linux-pm@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Anup Patel <anup.patel@wdc.com>
Subject: Re: [PATCH v8 1/8] RISC-V: Enable CPU_IDLE drivers
Date: Tue, 12 Oct 2021 06:24:07 +0530 [thread overview]
Message-ID: <CAAhSdy0C6rcavMiPgzxejrxevjvorM=BWbtO8gLMTATSg9DUHg@mail.gmail.com> (raw)
In-Reply-To: <30695639.mNO2d7px6N@diego>
On Tue, Oct 12, 2021 at 3:34 AM Heiko Stübner <heiko@sntech.de> wrote:
>
> Hi Anup,
>
> Am Montag, 11. Oktober 2021, 10:18:13 CEST schrieb Anup Patel:
> > We force select CPU_PM and provide asm/cpuidle.h so that we can
> > use CPU IDLE drivers for Linux RISC-V kernel.
> >
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > ---
> > arch/riscv/Kconfig | 7 +++++++
> > arch/riscv/configs/defconfig | 1 +
> > arch/riscv/configs/rv32_defconfig | 1 +
> > arch/riscv/include/asm/cpuidle.h | 24 ++++++++++++++++++++++++
> > arch/riscv/kernel/process.c | 3 ++-
> > 5 files changed, 35 insertions(+), 1 deletion(-)
> > create mode 100644 arch/riscv/include/asm/cpuidle.h
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 8de2afb460f7..d02f1f5a2431 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -46,6 +46,7 @@ config RISCV
> > select CLONE_BACKWARDS
> > select CLINT_TIMER if !MMU
> > select COMMON_CLK
> > + select CPU_PM if CPU_IDLE
> > select EDAC_SUPPORT
> > select GENERIC_ARCH_TOPOLOGY if SMP
> > select GENERIC_ATOMIC64 if !64BIT
> > @@ -564,5 +565,11 @@ source "kernel/power/Kconfig"
> >
> > endmenu
> >
> > +menu "CPU Power Management"
> > +
> > +source "drivers/cpuidle/Kconfig"
> > +
> > +endmenu
> > +
> > source "arch/riscv/kvm/Kconfig"
> > source "drivers/firmware/Kconfig"
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index be21f54e9b91..39b4c32e7997 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -20,6 +20,7 @@ CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_VIRT=y
> > CONFIG_SMP=y
> > CONFIG_HOTPLUG_CPU=y
> > +CONFIG_CPU_IDLE=y
> > CONFIG_VIRTUALIZATION=y
> > CONFIG_KVM=y
> > CONFIG_JUMP_LABEL=y
>
> This doesn't apply.
>
> In the history of your tree that you referenced in the cover-letter
> I found "RISC-V: Enable KVM for RV64 and RV32"
> with that nice "DO NOT UPSTREAM !!!!!" message in caps in it ;-)
>
> This of course makes this not apply on the main riscv tree.
>
> So you might want to base your series on top of a clean "for-next"
> branch of Palmer's tree instead of collecting other stuff below it.
I usually base everything on the most recent Linus release tag.
This time I accidentally rebased on my KVM RISC-V branch which
was merged recently.
I will anyway send v9.
Regards,
Anup
>
> Same for rv32_defconfig below.
>
>
> Heiko
>
>
> > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> > index ad01f50c98f1..fed827c82a9e 100644
> > --- a/arch/riscv/configs/rv32_defconfig
> > +++ b/arch/riscv/configs/rv32_defconfig
> > @@ -20,6 +20,7 @@ CONFIG_SOC_VIRT=y
> > CONFIG_ARCH_RV32I=y
> > CONFIG_SMP=y
> > CONFIG_HOTPLUG_CPU=y
> > +CONFIG_CPU_IDLE=y
> > CONFIG_VIRTUALIZATION=y
> > CONFIG_KVM=y
> > CONFIG_JUMP_LABEL=y
> > diff --git a/arch/riscv/include/asm/cpuidle.h b/arch/riscv/include/asm/cpuidle.h
> > new file mode 100644
> > index 000000000000..71fdc607d4bc
> > --- /dev/null
> > +++ b/arch/riscv/include/asm/cpuidle.h
> > @@ -0,0 +1,24 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (C) 2021 Allwinner Ltd
> > + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> > + */
> > +
> > +#ifndef _ASM_RISCV_CPUIDLE_H
> > +#define _ASM_RISCV_CPUIDLE_H
> > +
> > +#include <asm/barrier.h>
> > +#include <asm/processor.h>
> > +
> > +static inline void cpu_do_idle(void)
> > +{
> > + /*
> > + * Add mb() here to ensure that all
> > + * IO/MEM accesses are completed prior
> > + * to entering WFI.
> > + */
> > + mb();
> > + wait_for_interrupt();
> > +}
> > +
> > +#endif
> > diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
> > index 03ac3aa611f5..504b496787aa 100644
> > --- a/arch/riscv/kernel/process.c
> > +++ b/arch/riscv/kernel/process.c
> > @@ -23,6 +23,7 @@
> > #include <asm/string.h>
> > #include <asm/switch_to.h>
> > #include <asm/thread_info.h>
> > +#include <asm/cpuidle.h>
> >
> > register unsigned long gp_in_global __asm__("gp");
> >
> > @@ -37,7 +38,7 @@ extern asmlinkage void ret_from_kernel_thread(void);
> >
> > void arch_cpu_idle(void)
> > {
> > - wait_for_interrupt();
> > + cpu_do_idle();
> > raw_local_irq_enable();
> > }
> >
> >
>
>
>
>
next prev parent reply other threads:[~2021-10-12 0:54 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-11 8:18 [PATCH v8 0/8] RISC-V CPU Idle Support Anup Patel
2021-10-11 8:18 ` [PATCH v8 1/8] RISC-V: Enable CPU_IDLE drivers Anup Patel
2021-10-11 22:04 ` Heiko Stübner
2021-10-12 0:54 ` Anup Patel [this message]
2021-10-11 23:16 ` Heiko Stübner
2021-10-12 0:57 ` Anup Patel
2021-10-11 8:18 ` [PATCH v8 2/8] RISC-V: Rename relocate() and make it global Anup Patel
2021-10-11 8:18 ` [PATCH v8 3/8] RISC-V: Add arch functions for non-retentive suspend entry/exit Anup Patel
2021-10-11 8:18 ` [PATCH v8 4/8] RISC-V: Add SBI HSM suspend related defines Anup Patel
2021-10-11 8:18 ` [PATCH v8 5/8] cpuidle: Factor-out power domain related code from PSCI domain driver Anup Patel
2021-10-11 8:18 ` [PATCH v8 6/8] cpuidle: Add RISC-V SBI CPU idle driver Anup Patel
2021-10-11 8:18 ` [PATCH v8 7/8] dt-bindings: Add common bindings for ARM and RISC-V idle states Anup Patel
2021-10-11 13:36 ` Rob Herring
2021-10-11 8:18 ` [PATCH v8 8/8] RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine Anup Patel
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