From: Anup Patel <anup@brainfault.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: linux-kernel@vger.kernel.org,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>, Guo Ren <guoren@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
kvm-riscv@lists.infradead.org, kvm@vger.kernel.org,
linux-riscv@lists.infradead.org,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Sergey Matyukevich <sergey.matyukevich@syntacore.com>,
Will Deacon <will@kernel.org>
Subject: Re: [PATCH v3 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode
Date: Sun, 29 Jan 2023 18:07:12 +0530 [thread overview]
Message-ID: <CAAhSdy0HG_0DZVLDF3Rvbofx-4P_2z7Tp+hGJ7VwgTH-u6uLGA@mail.gmail.com> (raw)
In-Reply-To: <20230127182558.2416400-11-atishp@rivosinc.com>
On Fri, Jan 27, 2023 at 11:56 PM Atish Patra <atishp@rivosinc.com> wrote:
>
> Any guest must not get access to any hpmcounter including cycle/instret
> without any checks. We achieve that by disabling all the bits except TM
> bit in hcounteren.
>
> However, instret and cycle access for guest user space can be enabled
> upon explicit request (via ONE REG) or on first trap from VU mode
> to maintain ABI requirement in the future. This patch doesn't support
> that as ONE REG interface is not settled yet.
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> arch/riscv/kvm/main.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
> index 58c5489..c5d400f 100644
> --- a/arch/riscv/kvm/main.c
> +++ b/arch/riscv/kvm/main.c
> @@ -49,7 +49,8 @@ int kvm_arch_hardware_enable(void)
> hideleg |= (1UL << IRQ_VS_EXT);
> csr_write(CSR_HIDELEG, hideleg);
>
> - csr_write(CSR_HCOUNTEREN, -1UL);
> + /* VS should access only the time counter directly. Everything else should trap */
> + csr_write(CSR_HCOUNTEREN, 0x02);
>
> csr_write(CSR_HVIP, 0);
>
> --
> 2.25.1
>
next prev parent reply other threads:[~2023-01-29 12:37 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-27 18:25 [PATCH v3 00/14] KVM perf support Atish Patra
2023-01-27 18:25 ` [PATCH v3 01/14] perf: RISC-V: Define helper functions expose hpm counter width and count Atish Patra
2023-01-28 14:44 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 02/14] perf: RISC-V: Improve privilege mode filtering for perf Atish Patra
2023-01-28 14:47 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 03/14] RISC-V: Improve SBI PMU extension related definitions Atish Patra
2023-01-27 22:53 ` Conor Dooley
2023-01-31 19:30 ` Atish Patra
2023-01-27 18:25 ` [PATCH v3 04/14] RISC-V: KVM: Define a probe function for SBI extension data structures Atish Patra
2023-01-28 14:50 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 05/14] RISC-V: KVM: Return correct code for hsm stop function Atish Patra
2023-01-28 14:52 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 06/14] RISC-V: KVM: Modify SBI extension handler to return SBI error code Atish Patra
2023-01-29 12:16 ` Anup Patel
2023-01-31 20:38 ` Atish Patra
2023-01-27 18:25 ` [PATCH v3 07/14] RISC-V: KVM: Add skeleton support for perf Atish Patra
2023-01-29 12:30 ` Anup Patel
2023-01-31 22:35 ` Atish Patra
2023-02-01 3:48 ` Anup Patel
2023-02-01 8:41 ` Atish Patra
2023-02-01 9:05 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 08/14] RISC-V: KVM: Add SBI PMU extension support Atish Patra
2023-01-29 12:34 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 09/14] RISC-V: KVM: Make PMU functionality depend on Sscofpmf Atish Patra
2023-01-29 12:35 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 10/14] RISC-V: KVM: Disable all hpmcounter access for VS/VU mode Atish Patra
2023-01-29 12:37 ` Anup Patel [this message]
2023-01-27 18:25 ` [PATCH v3 11/14] RISC-V: KVM: Implement trap & emulate for hpmcounters Atish Patra
2023-01-29 12:44 ` Anup Patel
2023-01-31 22:46 ` Atish Patra
2023-02-01 8:58 ` Atish Patra
2023-02-01 9:09 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 12/14] RISC-V: KVM: Implement perf support without sampling Atish Patra
2023-01-30 15:40 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 13/14] RISC-V: KVM: Support firmware events Atish Patra
2023-01-30 15:47 ` Anup Patel
2023-01-27 18:25 ` [PATCH v3 14/14] RISC-V: KVM: Increment firmware pmu events Atish Patra
2023-01-30 15:48 ` Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAAhSdy0HG_0DZVLDF3Rvbofx-4P_2z7Tp+hGJ7VwgTH-u6uLGA@mail.gmail.com \
--to=anup@brainfault.org \
--cc=ajones@ventanamicro.com \
--cc=atishp@atishpatra.org \
--cc=atishp@rivosinc.com \
--cc=guoren@kernel.org \
--cc=heiko@sntech.de \
--cc=kvm-riscv@lists.infradead.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=mark.rutland@arm.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=sergey.matyukevich@syntacore.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).