* [PATCH] riscv: force __cpu_up_ variables to put in data section
@ 2020-04-30 9:53 Zong Li
2020-04-30 14:45 ` Greentime Hu
2020-04-30 18:22 ` Atish Patra
0 siblings, 2 replies; 6+ messages in thread
From: Zong Li @ 2020-04-30 9:53 UTC (permalink / raw)
To: paul.walmsley, palmer, linux-riscv, linux-kernel; +Cc: Zong Li
Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
Currently, these two variables are put in bss section, there is a
potential risk that secondary harts get the uninitialized value before
main hart finishing the bss clearing. In this case, all secondary
harts would go through the waiting loop and enable the MMU before
main hart set up the page table.
Signed-off-by: Zong Li <zong.li@sifive.com>
---
arch/riscv/kernel/cpu_ops.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
index c4c33bf02369..0ec22354018c 100644
--- a/arch/riscv/kernel/cpu_ops.c
+++ b/arch/riscv/kernel/cpu_ops.c
@@ -15,8 +15,8 @@
const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
-void *__cpu_up_stack_pointer[NR_CPUS];
-void *__cpu_up_task_pointer[NR_CPUS];
+void *__cpu_up_stack_pointer[NR_CPUS] __section(.data);
+void *__cpu_up_task_pointer[NR_CPUS] __section(.data);
extern const struct cpu_operations cpu_ops_sbi;
extern const struct cpu_operations cpu_ops_spinwait;
--
2.26.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: force __cpu_up_ variables to put in data section
2020-04-30 9:53 [PATCH] riscv: force __cpu_up_ variables to put in data section Zong Li
@ 2020-04-30 14:45 ` Greentime Hu
2020-04-30 18:22 ` Atish Patra
1 sibling, 0 replies; 6+ messages in thread
From: Greentime Hu @ 2020-04-30 14:45 UTC (permalink / raw)
To: Zong Li
Cc: Paul Walmsley, Palmer Dabbelt, linux-riscv, Linux Kernel Mailing List
Zong Li <zong.li@sifive.com> 於 2020年4月30日 週四 下午5:53寫道：
>
> Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
> Currently, these two variables are put in bss section, there is a
> potential risk that secondary harts get the uninitialized value before
> main hart finishing the bss clearing. In this case, all secondary
> harts would go through the waiting loop and enable the MMU before
> main hart set up the page table.
>
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
> arch/riscv/kernel/cpu_ops.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
> index c4c33bf02369..0ec22354018c 100644
> --- a/arch/riscv/kernel/cpu_ops.c
> +++ b/arch/riscv/kernel/cpu_ops.c
> @@ -15,8 +15,8 @@
>
> const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
>
> -void *__cpu_up_stack_pointer[NR_CPUS];
> -void *__cpu_up_task_pointer[NR_CPUS];
> +void *__cpu_up_stack_pointer[NR_CPUS] __section(.data);
> +void *__cpu_up_task_pointer[NR_CPUS] __section(.data);
>
> extern const struct cpu_operations cpu_ops_sbi;
> extern const struct cpu_operations cpu_ops_spinwait;
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: force __cpu_up_ variables to put in data section
2020-04-30 9:53 [PATCH] riscv: force __cpu_up_ variables to put in data section Zong Li
2020-04-30 14:45 ` Greentime Hu
@ 2020-04-30 18:22 ` Atish Patra
2020-05-02 6:00 ` Zong Li
1 sibling, 1 reply; 6+ messages in thread
From: Atish Patra @ 2020-04-30 18:22 UTC (permalink / raw)
To: Zong Li
Cc: Paul Walmsley, Palmer Dabbelt, linux-riscv,
linux-kernel@vger.kernel.org List
On Thu, Apr 30, 2020 at 2:53 AM Zong Li <zong.li@sifive.com> wrote:
>
> Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
> Currently, these two variables are put in bss section, there is a
> potential risk that secondary harts get the uninitialized value before
> main hart finishing the bss clearing. In this case, all secondary
> harts would go through the waiting loop and enable the MMU before
> main hart set up the page table.
>
That would be only true if you are using random booting protocol with
SBI v0.1 implementation.
With HSM extension in place, all the secondary cores are waiting in
firmware. The booting core
will bring them up one by one from cpu_up method.
The HSM extension is already available in OpenSBI v0.7 and Linux
kernel 5.7-rc1 onwards.
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
> arch/riscv/kernel/cpu_ops.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
> index c4c33bf02369..0ec22354018c 100644
> --- a/arch/riscv/kernel/cpu_ops.c
> +++ b/arch/riscv/kernel/cpu_ops.c
> @@ -15,8 +15,8 @@
>
> const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
>
> -void *__cpu_up_stack_pointer[NR_CPUS];
> -void *__cpu_up_task_pointer[NR_CPUS];
> +void *__cpu_up_stack_pointer[NR_CPUS] __section(.data);
> +void *__cpu_up_task_pointer[NR_CPUS] __section(.data);
>
> extern const struct cpu_operations cpu_ops_sbi;
> extern const struct cpu_operations cpu_ops_spinwait;
> --
> 2.26.1
>
>
--
Regards,
Atish
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: force __cpu_up_ variables to put in data section
2020-04-30 18:22 ` Atish Patra
@ 2020-05-02 6:00 ` Zong Li
2020-05-02 6:13 ` Anup Patel
0 siblings, 1 reply; 6+ messages in thread
From: Zong Li @ 2020-05-02 6:00 UTC (permalink / raw)
To: Atish Patra
Cc: Paul Walmsley, Palmer Dabbelt, linux-riscv,
linux-kernel@vger.kernel.org List
On Fri, May 1, 2020 at 2:23 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Thu, Apr 30, 2020 at 2:53 AM Zong Li <zong.li@sifive.com> wrote:
> >
> > Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
> > Currently, these two variables are put in bss section, there is a
> > potential risk that secondary harts get the uninitialized value before
> > main hart finishing the bss clearing. In this case, all secondary
> > harts would go through the waiting loop and enable the MMU before
> > main hart set up the page table.
> >
>
> That would be only true if you are using random booting protocol with
> SBI v0.1 implementation.
> With HSM extension in place, all the secondary cores are waiting in
> firmware. The booting core
> will bring them up one by one from cpu_up method.
>
> The HSM extension is already available in OpenSBI v0.7 and Linux
> kernel 5.7-rc1 onwards.
If I understand correctly, the newest kernel still works with earlier
OpenSBI than v0.7 or BBL. It seems to me that we need to consider the
use cases if we don't limit it to up to OpenSBI v0.7.
>
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> > arch/riscv/kernel/cpu_ops.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c
> > index c4c33bf02369..0ec22354018c 100644
> > --- a/arch/riscv/kernel/cpu_ops.c
> > +++ b/arch/riscv/kernel/cpu_ops.c
> > @@ -15,8 +15,8 @@
> >
> > const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init;
> >
> > -void *__cpu_up_stack_pointer[NR_CPUS];
> > -void *__cpu_up_task_pointer[NR_CPUS];
> > +void *__cpu_up_stack_pointer[NR_CPUS] __section(.data);
> > +void *__cpu_up_task_pointer[NR_CPUS] __section(.data);
> >
> > extern const struct cpu_operations cpu_ops_sbi;
> > extern const struct cpu_operations cpu_ops_spinwait;
> > --
> > 2.26.1
> >
> >
>
>
> --
> Regards,
> Atish
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: force __cpu_up_ variables to put in data section
2020-05-02 6:00 ` Zong Li
@ 2020-05-02 6:13 ` Anup Patel
2020-05-02 9:49 ` Zong Li
0 siblings, 1 reply; 6+ messages in thread
From: Anup Patel @ 2020-05-02 6:13 UTC (permalink / raw)
To: Zong Li
Cc: Atish Patra, linux-riscv, Palmer Dabbelt,
linux-kernel@vger.kernel.org List, Paul Walmsley
On Sat, May 2, 2020 at 11:30 AM Zong Li <zong.li@sifive.com> wrote:
>
> On Fri, May 1, 2020 at 2:23 AM Atish Patra <atishp@atishpatra.org> wrote:
> >
> > On Thu, Apr 30, 2020 at 2:53 AM Zong Li <zong.li@sifive.com> wrote:
> > >
> > > Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
> > > Currently, these two variables are put in bss section, there is a
> > > potential risk that secondary harts get the uninitialized value before
> > > main hart finishing the bss clearing. In this case, all secondary
> > > harts would go through the waiting loop and enable the MMU before
> > > main hart set up the page table.
> > >
> >
> > That would be only true if you are using random booting protocol with
> > SBI v0.1 implementation.
> > With HSM extension in place, all the secondary cores are waiting in
> > firmware. The booting core
> > will bring them up one by one from cpu_up method.
> >
> > The HSM extension is already available in OpenSBI v0.7 and Linux
> > kernel 5.7-rc1 onwards.
>
> If I understand correctly, the newest kernel still works with earlier
> OpenSBI than v0.7 or BBL. It seems to me that we need to consider the
> use cases if we don't limit it to up to OpenSBI v0.7.
I think the commit description should clearly state that the issue will
manifest only for random booting of multiple HARTs which means it
will manifest only for BBL and OpenSBI v0.6 (or older).
Regards,
Anup
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] riscv: force __cpu_up_ variables to put in data section
2020-05-02 6:13 ` Anup Patel
@ 2020-05-02 9:49 ` Zong Li
0 siblings, 0 replies; 6+ messages in thread
From: Zong Li @ 2020-05-02 9:49 UTC (permalink / raw)
To: Anup Patel
Cc: Atish Patra, linux-riscv, Palmer Dabbelt,
linux-kernel@vger.kernel.org List, Paul Walmsley
On Sat, May 2, 2020 at 2:13 PM Anup Patel <anup@brainfault.org> wrote:
>
> On Sat, May 2, 2020 at 11:30 AM Zong Li <zong.li@sifive.com> wrote:
> >
> > On Fri, May 1, 2020 at 2:23 AM Atish Patra <atishp@atishpatra.org> wrote:
> > >
> > > On Thu, Apr 30, 2020 at 2:53 AM Zong Li <zong.li@sifive.com> wrote:
> > > >
> > > > Put __cpu_up_stack_pointer and __cpu_up_task_pointer in data section.
> > > > Currently, these two variables are put in bss section, there is a
> > > > potential risk that secondary harts get the uninitialized value before
> > > > main hart finishing the bss clearing. In this case, all secondary
> > > > harts would go through the waiting loop and enable the MMU before
> > > > main hart set up the page table.
> > > >
> > >
> > > That would be only true if you are using random booting protocol with
> > > SBI v0.1 implementation.
> > > With HSM extension in place, all the secondary cores are waiting in
> > > firmware. The booting core
> > > will bring them up one by one from cpu_up method.
> > >
> > > The HSM extension is already available in OpenSBI v0.7 and Linux
> > > kernel 5.7-rc1 onwards.
> >
> > If I understand correctly, the newest kernel still works with earlier
> > OpenSBI than v0.7 or BBL. It seems to me that we need to consider the
> > use cases if we don't limit it to up to OpenSBI v0.7.
>
> I think the commit description should clearly state that the issue will
> manifest only for random booting of multiple HARTs which means it
> will manifest only for BBL and OpenSBI v0.6 (or older).
>
OK. Let me modify the description. Thanks.
> Regards,
> Anup
^ permalink raw reply [flat|nested] 6+ messages in thread
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2020-04-30 9:53 [PATCH] riscv: force __cpu_up_ variables to put in data section Zong Li
2020-04-30 14:45 ` Greentime Hu
2020-04-30 18:22 ` Atish Patra
2020-05-02 6:00 ` Zong Li
2020-05-02 6:13 ` Anup Patel
2020-05-02 9:49 ` Zong Li
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