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charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jun 7, 2019 at 11:31 AM Anup Patel wrote: > > This patchset implements two-stagged initial page table setup using fixmap > to avoid mapping non-existent RAM and also reduce high_memory consumed by > initial page tables. > > The patchset is based on Linux-5.2-rc3 and tested on SiFive Unleashed board > and QEMU virt machine. > > These patches can be found in riscv_setup_vm_v5 branch of > https//github.com/avpatel/linux.git > > Changes since v4: > - Added dtb_early_va which points to DTB for early parsing > > Changes since v3: > - Changed patch series subject. > - Dropped PATCH1 because it's already merged > - Dropped PATCH3 because trampoline page table handles a corner case > for 32bit systems where load address range overlaps kernel virtual > address range > - Revamped PATCH for 4K aligned booting into two-stagged initial page > table setup > > Changes since v2: > - Dropped PATCH2 because we have separate fix for Linux-5.1-rcX > - Moved PATCH5 to PATCH2 > - Moved PATCH4 to PATCH3 > - The "Booting kernel from any 4KB aligned address" is now PATCH4 > > Changes since v1: > - Add kconfig option BOOT_PAGE_ALIGNED to enable 4KB aligned booting > - Improved initial page table setup code to select best/biggest > possible mapping size based on load address alignment > - Added PATCH4 to remove redundant trampoline page table > - Added PATCH5 to fix memory reservation in setup_bootmem() > > Anup Patel (2): > RISC-V: Fix memory reservation in setup_bootmem() > RISC-V: Setup initial page tables in two stages > > arch/riscv/include/asm/fixmap.h | 5 + > arch/riscv/include/asm/pgtable-64.h | 5 + > arch/riscv/include/asm/pgtable.h | 8 + > arch/riscv/kernel/head.S | 17 +- > arch/riscv/kernel/setup.c | 6 +- > arch/riscv/mm/init.c | 331 ++++++++++++++++++++++------ > 6 files changed, 292 insertions(+), 80 deletions(-) > > -- > 2.17.1 Hi All, Any comments on this series? Regards, Anup