From: Anup Patel <anup@brainfault.org>
To: Palmer Dabbelt <palmer@rivosinc.com>
Cc: linux-riscv <linux-riscv@lists.infradead.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup.patel@wdc.com>,
Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
Atish Patra <atish.patra@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Sagar Shrikant Kadam <sagar.kadam@sifive.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
axboe@kernel.dk,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
stable@vger.kernel.org
Subject: Re: [PATCH 02/12] RISC-V: MAXPHYSMEM_2GB doesn't depend on CMODEL_MEDLOW
Date: Sat, 20 Nov 2021 09:27:09 +0530 [thread overview]
Message-ID: <CAAhSdy1hx3Me_YCKnE=QkTaA9j-qyZjmgJDM8nT-uYCdg7vf=g@mail.gmail.com> (raw)
In-Reply-To: <20211119164413.29052-3-palmer@rivosinc.com>
On Fri, Nov 19, 2021 at 10:14 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> From: Palmer Dabbelt <palmer@rivosinc.com>
>
> For non-relocatable kernels we need to be able to link the kernel at
> approximately PAGE_OFFSET, thus requiring medany (as medlow requires the
> code to be linked within 2GiB of 0). The inverse doesn't apply, though:
> since medany code can be linked anywhere it's fine to link it close to
> 0, so we can support the smaller memory config.
>
> Fixes: de5f4b8f634b ("RISC-V: Define MAXPHYSMEM_1GB only for RV32")
> Cc: stable@vger.kernel.org
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
>
> ---
>
> I found this when going through the savedefconfig diffs for the K210
> defconfigs. I'm not entirely sure they're doing the right thing here
> (they should probably be setting CMODEL_LOW to take advantage of the
> better code generation), but I don't have any way to test those
> platforms so I don't want to change too much.
> ---
> arch/riscv/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 821252b65f89..61f64512dcde 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -280,7 +280,7 @@ choice
> depends on 32BIT
> bool "1GiB"
> config MAXPHYSMEM_2GB
> - depends on 64BIT && CMODEL_MEDLOW
> + depends on 64BIT
> bool "2GiB"
> config MAXPHYSMEM_128GB
> depends on 64BIT && CMODEL_MEDANY
> --
> 2.32.0
>
next prev parent reply other threads:[~2021-11-20 3:57 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-19 16:44 [PATCH 0/12] RISC-V: Clean up the defconfigs Palmer Dabbelt
2021-11-19 16:44 ` [PATCH 01/12] RISC-V: defconfigs: Set CONFIG_FB=y, for FB console Palmer Dabbelt
2021-11-20 3:56 ` Anup Patel
2021-11-19 16:44 ` [PATCH 02/12] RISC-V: MAXPHYSMEM_2GB doesn't depend on CMODEL_MEDLOW Palmer Dabbelt
2021-11-20 3:57 ` Anup Patel [this message]
2022-01-11 16:04 ` Geert Uytterhoeven
2022-01-11 16:14 ` Alexandre ghiti
2022-01-14 10:12 ` Geert Uytterhoeven
2022-01-14 11:11 ` Alexandre Ghiti
2022-01-14 8:40 ` Conor.Dooley
2022-01-14 9:09 ` Alexandre ghiti
2022-01-14 9:41 ` Conor.Dooley
2022-01-14 9:45 ` Alexandre Ghiti
2021-11-19 16:44 ` [PATCH 03/12] RISC-V: defconfigs: Sort CONFIG_BPF_SYSCALL Palmer Dabbelt
2021-11-20 3:58 ` Anup Patel
2021-11-19 16:44 ` [PATCH 04/12] RISC-V: defconfigs: Sort CONFIG_SYSFS_SYSCALL Palmer Dabbelt
2021-11-20 3:58 ` Anup Patel
2021-11-19 16:44 ` [PATCH 05/12] RISC-V: defconfigs: Sort CONFIG_SOC_POLARFIRE Palmer Dabbelt
2021-11-20 3:59 ` Anup Patel
2021-11-19 16:44 ` [PATCH 06/12] RISC-V: defconfigs: Sort CONFIG_PTP_1588_CLOCK Palmer Dabbelt
2021-11-20 4:00 ` Anup Patel
2021-11-19 16:44 ` [PATCH 07/12] RISC-V: defconfigs: Sort CONFIG_MMC Palmer Dabbelt
2021-11-20 4:01 ` Anup Patel
2021-11-19 16:44 ` [PATCH 08/12] RISC-V: defconfigs: Sort CONFIG_SURFACE_PLATFORMS Palmer Dabbelt
2021-11-20 4:02 ` Anup Patel
2021-11-19 16:44 ` [PATCH 09/12] RISC-V: defconfigs: Sort CONFIG_BLK_DEV_BSG Palmer Dabbelt
2021-11-20 4:04 ` Anup Patel
2021-11-19 16:44 ` [PATCH 10/12] RISC-V: defconfigs: Remove redundant CONFIG_POWER_RESET Palmer Dabbelt
2021-11-20 4:04 ` Anup Patel
2021-11-19 16:44 ` [PATCH 11/12] RISC-V: defconfigs: Remove redundant CONFIG_EFI=y Palmer Dabbelt
2021-11-20 4:05 ` Anup Patel
2021-11-19 16:44 ` [PATCH 12/12] RISC-V: defconfigs: Remove redundant K210 DT source Palmer Dabbelt
2021-11-20 4:07 ` Anup Patel
2021-11-21 23:41 ` Damien Le Moal
2022-01-06 18:01 ` Palmer Dabbelt
2022-01-07 2:14 ` Damien Le Moal
2022-01-20 18:19 ` Palmer Dabbelt
2022-01-20 23:33 ` Damien Le Moal
2021-11-20 4:11 ` [PATCH 0/12] RISC-V: Clean up the defconfigs Anup Patel
2021-11-22 2:45 ` Bin Meng
2022-01-06 18:01 ` Palmer Dabbelt
2021-11-21 23:47 ` Damien Le Moal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAAhSdy1hx3Me_YCKnE=QkTaA9j-qyZjmgJDM8nT-uYCdg7vf=g@mail.gmail.com' \
--to=anup@brainfault.org \
--cc=anup.patel@wdc.com \
--cc=aou@eecs.berkeley.edu \
--cc=atish.patra@wdc.com \
--cc=axboe@kernel.dk \
--cc=bin.meng@windriver.com \
--cc=damien.lemoal@wdc.com \
--cc=heinrich.schuchardt@canonical.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=palmer@rivosinc.com \
--cc=paul.walmsley@sifive.com \
--cc=sagar.kadam@sifive.com \
--cc=stable@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).