From: Anup Patel <anup@brainfault.org>
To: Christian Borntraeger <borntraeger@de.ibm.com>
Cc: Anup Patel <Anup.Patel@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Paolo Bonzini <pbonzini@redhat.com>, Radim K <rkrcmar@redhat.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Atish Patra <Atish.Patra@wdc.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Damien Le Moal <Damien.LeMoal@wdc.com>,
Christoph Hellwig <hch@infradead.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RFC PATCH v2 07/19] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls
Date: Mon, 5 Aug 2019 17:26:21 +0530 [thread overview]
Message-ID: <CAAhSdy2PDSpTy1JEEC2LCB4ESvZHBbkVEZ2wqz-D2b7SKD5VSg@mail.gmail.com> (raw)
In-Reply-To: <edbed85f-f7ad-a240-1bef-75729b527a69@de.ibm.com>
On Mon, Aug 5, 2019 at 5:08 PM Christian Borntraeger
<borntraeger@de.ibm.com> wrote:
>
>
>
> On 02.08.19 09:47, Anup Patel wrote:
> > For KVM RISC-V, we use KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls to access
> > VCPU config and registers from user-space.
> >
> > We have three types of VCPU registers:
> > 1. CONFIG - these are VCPU config and capabilities
> > 2. CORE - these are VCPU general purpose registers
> > 3. CSR - these are VCPU control and status registers
> >
> > The CONFIG registers available to user-space are ISA and TIMEBASE. Out
> > of these, TIMEBASE is a read-only register which inform user-space about
> > VCPU timer base frequency. The ISA register is a read and write register
> > where user-space can only write the desired VCPU ISA capabilities before
> > running the VCPU.
> >
> > The CORE registers available to user-space are PC, RA, SP, GP, TP, A0-A7,
> > T0-T6, S0-S11 and MODE. Most of these are RISC-V general registers except
> > PC and MODE. The PC register represents program counter whereas the MODE
> > register represent VCPU privilege mode (i.e. S/U-mode).
> >
> > The CSRs available to user-space are SSTATUS, SIE, STVEC, SSCRATCH, SEPC,
> > SCAUSE, STVAL, SIP, and SATP. All of these are read/write registers.
> >
> > In future, more VCPU register types will be added (such as FP) for the
> > KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls.
>
> While have ONE_REG will certainly work, have you considered the sync_reg scheme
> (registers as part of kvm_run structure)
> This will speed up the exit to QEMU as you do not have to do multiple ioctls
> (each imposing a systemcall overhead) for one exit.
>
> Ideally you should not exit too often into qemu, but for those cases sync_regs
> is faster than ONE_REG.
>
We will certainly explore sync_regs interface. Reducing exits to user-space
will definitely help.
This is the first series for KVM RISC-V so here we want to establish a stable
and extensible UAPI header using which we will add support to QEMU KVM.
For time being, we are using KVMTOOL for debug and development.
Thanks,
Anup
next prev parent reply other threads:[~2019-08-05 11:56 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-02 7:46 [RFC PATCH v2 00/19] KVM RISC-V Support Anup Patel
2019-08-02 7:47 ` [RFC PATCH v2 01/19] KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface Anup Patel
2019-08-02 7:47 ` [RFC PATCH v2 02/19] RISC-V: Export few kernel symbols Anup Patel
2019-08-02 7:47 ` [RFC PATCH v2 03/19] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2019-08-02 7:47 ` [RFC PATCH v2 04/19] RISC-V: Add initial skeletal KVM support Anup Patel
2019-08-02 9:01 ` Paolo Bonzini
2019-08-05 5:48 ` Anup Patel
2019-08-02 7:47 ` [RFC PATCH v2 05/19] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2019-08-02 7:47 ` [RFC PATCH v2 06/19] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2019-08-02 8:17 ` Paolo Bonzini
2019-08-05 12:27 ` Anup Patel
2019-08-02 7:47 ` [RFC PATCH v2 07/19] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2019-08-02 9:03 ` Paolo Bonzini
2019-08-05 6:55 ` Anup Patel
2019-08-05 7:10 ` Paolo Bonzini
2019-08-05 11:00 ` Anup Patel
2019-08-05 11:07 ` Paolo Bonzini
2019-08-05 11:37 ` Christian Borntraeger
2019-08-05 11:56 ` Anup Patel [this message]
2019-08-05 12:01 ` Paolo Bonzini
2019-08-05 12:13 ` Anup Patel
2019-08-05 11:56 ` Paolo Bonzini
2019-08-02 7:47 ` [RFC PATCH v2 08/19] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2019-08-02 8:30 ` Paolo Bonzini
2019-08-02 8:43 ` Anup Patel
2019-08-02 8:59 ` Paolo Bonzini
2019-08-02 7:47 ` [RFC PATCH v2 09/19] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2019-08-02 7:47 ` [RFC PATCH v2 10/19] RISC-V: KVM: Handle WFI " Anup Patel
2019-08-02 9:03 ` Paolo Bonzini
2019-08-05 7:12 ` Anup Patel
2019-08-05 7:14 ` Paolo Bonzini
2019-08-05 7:18 ` Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 11/19] RISC-V: KVM: Implement VMID allocator Anup Patel
2019-08-02 9:19 ` Paolo Bonzini
2019-08-05 10:07 ` Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 12/19] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2019-08-02 9:14 ` Paolo Bonzini
2019-08-05 10:08 ` Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 13/19] RISC-V: KVM: Implement MMU notifiers Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 14/19] RISC-V: KVM: Add timer functionality Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 15/19] RISC-V: KVM: FP lazy save/restore Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 16/19] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 17/19] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 18/19] RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig Anup Patel
2019-08-02 7:48 ` [RFC PATCH v2 19/19] RISC-V: KVM: Add MAINTAINERS entry Anup Patel
2019-08-02 9:22 ` [RFC PATCH v2 00/19] KVM RISC-V Support Paolo Bonzini
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