From: Anup Patel <anup@brainfault.org>
To: Andrew Jones <ajones@ventanamicro.com>
Cc: Anup Patel <apatel@ventanamicro.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid
Date: Sat, 3 Dec 2022 17:48:54 +0530 [thread overview]
Message-ID: <CAAhSdy3CnkK7=zombN4zH=g8+buz_rEhgXCzOE-WdSTYtcfdMA@mail.gmail.com> (raw)
In-Reply-To: <20221129054616.4zju5z7ipg6wki7l@kamzik>
On Tue, Nov 29, 2022 at 11:16 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> On Mon, Nov 28, 2022 at 09:44:23PM +0530, Anup Patel wrote:
> > We add ONE_REG interface for VCPU mvendorid, marchid, and mimpid
> > so that KVM user-space can change this details to support migration
> > across heterogeneous hosts.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > arch/riscv/include/uapi/asm/kvm.h | 3 +++
> > arch/riscv/kvm/vcpu.c | 27 +++++++++++++++++++++++++++
> > 2 files changed, 30 insertions(+)
> >
> > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> > index 8985ff234c01..92af6f3f057c 100644
> > --- a/arch/riscv/include/uapi/asm/kvm.h
> > +++ b/arch/riscv/include/uapi/asm/kvm.h
> > @@ -49,6 +49,9 @@ struct kvm_sregs {
> > struct kvm_riscv_config {
> > unsigned long isa;
> > unsigned long zicbom_block_size;
> > + unsigned long mvendorid;
> > + unsigned long marchid;
> > + unsigned long mimpid;
> > };
> >
> > /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> > diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> > index 312a8a926867..7c08567097f0 100644
> > --- a/arch/riscv/kvm/vcpu.c
> > +++ b/arch/riscv/kvm/vcpu.c
> > @@ -276,6 +276,15 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
> > return -EINVAL;
> > reg_val = riscv_cbom_block_size;
> > break;
> > + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> > + reg_val = vcpu->arch.mvendorid;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(marchid):
> > + reg_val = vcpu->arch.marchid;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> > + reg_val = vcpu->arch.mimpid;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > @@ -338,6 +347,24 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
> > break;
> > case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
> > return -EOPNOTSUPP;
> > + case KVM_REG_RISCV_CONFIG_REG(mvendorid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.mvendorid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(marchid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.marchid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > + case KVM_REG_RISCV_CONFIG_REG(mimpid):
> > + if (!vcpu->arch.ran_atleast_once)
> > + vcpu->arch.mimpid = reg_val;
> > + else
> > + return -EBUSY;
> > + break;
> > default:
> > return -EINVAL;
> > }
> > --
> > 2.34.1
> >
>
> At some point we should patch Documentation/virt/kvm/api.rst to describe
> the possible errors we have. It's missing EOPNOTSUPP and EBUSY.
>
> Also, I see a couple places were we use EOPNOTSUPP that would be better
> as EBUSY. And finally I wonder if we shouldn't use ENOENT when the reg_num
> is wrong/unknown, which would allow us to differentiate between bad
> reg_num and bad reg_val in set-one ioctls.
>
> I can send an RFC series to better describe these thoughts.
Sure, go ahead.
>
> And for this patch,
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
>
> Thanks,
> drew
Regards,
Anup
next prev parent reply other threads:[~2022-12-03 12:19 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-28 16:14 [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI Anup Patel
2022-11-28 16:14 ` [PATCH 1/9] RISC-V: KVM: Fix reg_val check in kvm_riscv_vcpu_set_reg_config() Anup Patel
2022-11-28 21:03 ` Atish Patra
2022-11-28 16:14 ` [PATCH 2/9] RISC-V: KVM: Remove redundant includes of asm/kvm_vcpu_timer.h Anup Patel
2022-11-28 21:04 ` Atish Patra
2022-11-29 5:20 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 3/9] RISC-V: KVM: Remove redundant includes of asm/csr.h Anup Patel
2022-11-28 21:04 ` Atish Patra
2022-11-28 16:14 ` [PATCH 4/9] RISC-V: KVM: Use switch-case in kvm_riscv_vcpu_set/get_reg() Anup Patel
2022-11-28 21:04 ` Atish Patra
2022-11-28 16:14 ` [PATCH 5/9] RISC-V: KVM: Move sbi related struct and functions to kvm_vcpu_sbi.h Anup Patel
2022-11-28 21:06 ` Atish Patra
2022-11-29 5:21 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 6/9] RISC-V: Export sbi_get_mvendorid() and friends Anup Patel
2022-11-28 21:07 ` Atish Patra
2022-12-09 4:33 ` Palmer Dabbelt
2022-11-29 5:21 ` Andrew Jones
2022-12-02 17:53 ` Palmer Dabbelt
2022-11-28 16:14 ` [PATCH 7/9] RISC-V: KVM: Save mvendorid, marchid, and mimpid when creating VCPU Anup Patel
2022-11-28 21:08 ` Atish Patra
2022-11-29 5:22 ` Andrew Jones
2022-11-28 16:14 ` [PATCH 8/9] RISC-V: KVM: Add ONE_REG interface for mvendorid, marchid, and mimpid Anup Patel
2022-11-28 21:09 ` Atish Patra
2022-11-29 5:46 ` Andrew Jones
2022-12-03 12:18 ` Anup Patel [this message]
2022-11-28 16:14 ` [PATCH 9/9] RISC-V: KVM: Add ONE_REG interface to enable/disable SBI extensions Anup Patel
2022-11-29 6:09 ` Andrew Jones
2022-12-03 12:39 ` [PATCH 0/9] RISC-V KVM ONE_REG interface for SBI Anup Patel
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