From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C496EC433F5 for ; Mon, 4 Oct 2021 04:47:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9FA6C61019 for ; Mon, 4 Oct 2021 04:47:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232516AbhJDEtQ (ORCPT ); Mon, 4 Oct 2021 00:49:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232358AbhJDEtP (ORCPT ); Mon, 4 Oct 2021 00:49:15 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 860D6C0613EC for ; Sun, 3 Oct 2021 21:47:26 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id e12so8226825wra.4 for ; Sun, 03 Oct 2021 21:47:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20210112.gappssmtp.com; s=20210112; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=f4tKoSTK3inceMY79QUe3y1d0IroqdLSv2OwkWk2/A8=; b=vWWDVV47UEHkiIDoYrLU082WRdmSUQHbaJsK0RBGw+i4JyXd9rB/yX9KmIKfNBBgm9 kqVPd0C9LMEc2i+5pNaKXcDDCWbt46i9W7lxZynQakH4aNdjNBs5+ST9hEs9h+4IkF7k zo4sMI9EwV/Y3h8sLXNIpcORk9a/qN4SlNmdlccZL2X0dIwAbpjEoYM6djVbFLGp+8ED K1HvhLZiW4DXx8nY3M3tc9sPnV3RNHd/O60P33ye2tcuQbhTDTXzUesV//3fymsnY6TD DM0GxD4TdxFNDbAXyFQateeN3vnqqyLU2JGij5IKaOn71GcK9c+QKQ36yjvCYBZwGFnR 1MaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=f4tKoSTK3inceMY79QUe3y1d0IroqdLSv2OwkWk2/A8=; b=Gb20w/NHPi8NzdOxNMDvQVqssNa7AFO9FU0dBNxxpSGYwUK/hWxm+xOcxUDRNuF4gV Wo/6vjU+1RAmvSWfHCKItXD2/qf9nPc9mwP7OzdzacRybxuhBdFs6hUlkUn8W/wbxboy G3511u/eGbtrFAVdBgVVE8W2AqNO2NaUN8hetMXtCiUQUoesECphSF2wqXdbYvIDd2wA ZRvnx3s14otUV+xCou457baNWBC8Gz0PTkkZH1Utq+bTjL+vwNgbvtDZZf1U4cfGPT1z tF+CF6TZgPCRMZR5gjyqGZ4WjYfFnw8SsV6k/CjMSTRPIxTSjLxCljIAC41WQvQ8AaqT qxYw== X-Gm-Message-State: AOAM5327Ad/r6hImOrwdEV9e/MlJwuVd4fug/ZIjkwTB35Kes/iPaz7l r32IL8PJudpBOqO6F7WiVTruq+NFFeYdAjKdIJVPXQ== X-Google-Smtp-Source: ABdhPJx37gv7S86waNUH+xL9Pa5+R4uyJSjSCccv/5SpnP1pbD+BHOOHyD+wYk5jf+xLYyO5QKxloQtS2nSz9VCP1U4= X-Received: by 2002:adf:ab57:: with SMTP id r23mr12045283wrc.199.1633322844751; Sun, 03 Oct 2021 21:47:24 -0700 (PDT) MIME-Version: 1.0 References: <20210927114016.1089328-1-anup.patel@wdc.com> In-Reply-To: From: Anup Patel Date: Mon, 4 Oct 2021 10:17:13 +0530 Message-ID: Subject: Re: [PATCH v20 00/17] KVM RISC-V Support To: Ley Foon Tan Cc: Palmer Dabbelt , Palmer Dabbelt , Paolo Bonzini , Paul Walmsley , Albert Ou , Alexander Graf , Atish Patra , Alistair Francis , Damien Le Moal , KVM General , kvm-riscv@lists.infradead.org, linux-riscv , "linux-kernel@vger.kernel.org List" , Anup Patel , Philipp Tomsich Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 4, 2021 at 7:58 AM Ley Foon Tan wrote: > > On Fri, Oct 1, 2021 at 6:41 PM Anup Patel wrote: > > > > On Fri, Oct 1, 2021 at 2:33 PM Ley Foon Tan wrote: > > > > > > On Mon, Sep 27, 2021 at 8:01 PM Anup Patel wrote: > > > > > > > > Hi Palmer, Hi Paolo, > > > > > > > > On Mon, Sep 27, 2021 at 5:10 PM Anup Patel wrote: > > > > > > > > > > This series adds initial KVM RISC-V support. Currently, we are able to boot > > > > > Linux on RV64/RV32 Guest with multiple VCPUs. > > > > > > > > > > Key aspects of KVM RISC-V added by this series are: > > > > > 1. No RISC-V specific KVM IOCTL > > > > > 2. Loadable KVM RISC-V module supported > > > > > 3. Minimal possible KVM world-switch which touches only GPRs and few CSRs > > > > > 4. Both RV64 and RV32 host supported > > > > > 5. Full Guest/VM switch is done via vcpu_get/vcpu_put infrastructure > > > > > 6. KVM ONE_REG interface for VCPU register access from user-space > > > > > 7. PLIC emulation is done in user-space > > > > > 8. Timer and IPI emuation is done in-kernel > > > > > 9. Both Sv39x4 and Sv48x4 supported for RV64 host > > > > > 10. MMU notifiers supported > > > > > 11. Generic dirtylog supported > > > > > 12. FP lazy save/restore supported > > > > > 13. SBI v0.1 emulation for KVM Guest available > > > > > 14. Forward unhandled SBI calls to KVM userspace > > > > > 15. Hugepage support for Guest/VM > > > > > 16. IOEVENTFD support for Vhost > > > > > > > > > > Here's a brief TODO list which we will work upon after this series: > > > > > 1. KVM unit test support > > > > > 2. KVM selftest support > > > > > 3. SBI v0.3 emulation in-kernel > > > > > 4. In-kernel PMU virtualization > > > > > 5. In-kernel AIA irqchip support > > > > > 6. Nested virtualizaiton > > > > > 7. ..... and more ..... > > > > > > > > > > This series can be found in riscv_kvm_v20 branch at: > > > > > https//github.com/avpatel/linux.git > > > > > > > > > > Our work-in-progress KVMTOOL RISC-V port can be found in riscv_v9 branch > > > > > at: https//github.com/avpatel/kvmtool.git > > > > > > > > > > The QEMU RISC-V hypervisor emulation is done by Alistair and is available > > > > > in master branch at: https://git.qemu.org/git/qemu.git > > > > > > > > > > To play around with KVM RISC-V, refer KVM RISC-V wiki at: > > > > > https://github.com/kvm-riscv/howto/wiki > > > > > https://github.com/kvm-riscv/howto/wiki/KVM-RISCV64-on-QEMU > > > > > https://github.com/kvm-riscv/howto/wiki/KVM-RISCV64-on-Spike > > > > > > Hi Anup > > It is able to boot up to kvm guest OS after change to use > https://github.com/avpatel/qemu.git, riscv_aia_v2 branch. > Is there dependency to AIA hardware feature for KVM? No, there is no dependency on AIA hardware and KVM RISC-V v20 series. I quickly tried the latest QEMU master with KVM RISC-V v20 and it worked perfectly fine for me. (QEMU master commit 30bd1db58b09c12b68c35f041f919014b885482d) Although, I did see that VS-mode interrupts were broken in the latest Spike due to some recent merge. I have sent fix PR to Spike for this. (Refer, https://github.com/riscv-software-src/riscv-isa-sim/pull/822) With Spike fix PR (above), the KVM RISC-V v20 series works fine on Spike as well. > > > Log: > > [ 6.212484] Run /virt/init as init process > Mounting... > [ 7.202552] random: fast init done > / # cat /proc/cpuinfo > processor : 0 > hart : 1 > isa : rv64imafdcsu > mmu : sv48 > > processor : 1 > hart : 0 > isa : rv64imafdcsu > mmu : sv48 > > / # cat /proc/interrupts > CPU0 CPU1 > 1: 355 0 SiFive PLIC 5 Edge virtio0 > 2: 212 0 SiFive PLIC 6 Edge virtio1 > 3: 11 0 SiFive PLIC 7 Edge virtio2 > 4: 155 0 SiFive PLIC 1 Edge ttyS0 > 5: 1150 942 RISC-V INTC 5 Edge riscv-timer > IPI0: 19 5 Rescheduling interrupts > IPI1: 50 565 Function call interrupts > IPI2: 0 0 CPU stop interrupts > IPI3: 0 0 IRQ work interrupts > IPI4: 0 0 Timer broadcast interrupts > > > Thanks. > > Regards > Ley Foon Regards, Anup