From: Anup Patel <anup@brainfault.org>
To: Atish Patra <atishp@rivosinc.com>
Cc: "linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
Atish Patra <atishp@atishpatra.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
DTML <devicetree@vger.kernel.org>,
Jisheng Zhang <jszhang@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
kvm-riscv@lists.infradead.org,
linux-riscv <linux-riscv@lists.infradead.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>
Subject: Re: [RFC PATCH v2 4/7] RISC-V: KVM: Remove 's' & 'u' as valid ISA extension
Date: Fri, 18 Mar 2022 08:55:56 +0530 [thread overview]
Message-ID: <CAAhSdy3bPuhqcZWpZpDP_DGiMEc97aMEjspum4K9k0D=24fYsg@mail.gmail.com> (raw)
In-Reply-To: <20220304201020.810380-5-atishp@rivosinc.com>
On Sat, Mar 5, 2022 at 1:40 AM Atish Patra <atishp@rivosinc.com> wrote:
>
> There are no ISA extension defined as 's' & 'u' in RISC-V specifications.
> The misa register defines 's' & 'u' bit as Supervisor/User privilege mode
> enabled. But it should not appear in the ISA extension in the device tree.
>
> Remove those from the allowed ISA extension for kvm.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Both PATCH4 and PATCH5, fix the "isa" config register of one_reg interface.
Can you send PATCH4 (i.e. this patch) and PATCH5 separately with the
"Fixes:" tag so that we can have these patches as RC fixes ?
Regards,
Anup
> ---
> arch/riscv/kvm/vcpu.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
> index 624166004e36..3ae545e7b398 100644
> --- a/arch/riscv/kvm/vcpu.c
> +++ b/arch/riscv/kvm/vcpu.c
> @@ -43,9 +43,7 @@ const struct kvm_stats_header kvm_vcpu_stats_header = {
> riscv_isa_extension_mask(d) | \
> riscv_isa_extension_mask(f) | \
> riscv_isa_extension_mask(i) | \
> - riscv_isa_extension_mask(m) | \
> - riscv_isa_extension_mask(s) | \
> - riscv_isa_extension_mask(u))
> + riscv_isa_extension_mask(m))
>
> static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
> {
> --
> 2.30.2
>
next prev parent reply other threads:[~2022-03-18 3:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-04 20:10 [RFC PATCH v2 0/7] Add Sstc extension support Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 1/7] RISC-V: Add SSTC extension CSR details Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 2/7] RISC-V: Enable sstc extension parsing from DT Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 3/7] RISC-V: Prefer sstc extension if available Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 4/7] RISC-V: KVM: Remove 's' & 'u' as valid ISA extension Atish Patra
2022-03-18 3:25 ` Anup Patel [this message]
2022-03-04 20:10 ` [RFC PATCH v2 5/7] RISC-V: KVM: Restrict the extensions that can be disabled Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 6/7] RISC-V: KVM: Introduce ISA extension register Atish Patra
2022-03-04 20:10 ` [RFC PATCH v2 7/7] RISC-V: KVM: Support sstc extension Atish Patra
2022-03-04 20:38 ` Jessica Clarke
2022-03-05 9:37 ` Atish Patra
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