From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752285AbeEQJFo (ORCPT ); Thu, 17 May 2018 05:05:44 -0400 Received: from mail-wm0-f67.google.com ([74.125.82.67]:52269 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751980AbeEQJFk (ORCPT ); Thu, 17 May 2018 05:05:40 -0400 X-Google-Smtp-Source: AB8JxZpAm8fh5Sl6BQJueGdDCMZsxIHi6TTGvUWafRYAIK2ujldmglyi2X2nCxXgg3DRdLEvUtQT+ENaGZbHAiegCUo= MIME-Version: 1.0 In-Reply-To: References: <7728da79-8a7a-b87d-d09c-b36978b3032e@linux.intel.com> From: Chris Chiu Date: Thu, 17 May 2018 17:05:38 +0800 Message-ID: Subject: Re: [BUG] i2c-hid: ELAN Touchpad does not work on ASUS X580GD To: Jarkko Nikula Cc: Daniel Drake , Jian-Hong Pan , Jiri Kosina , Benjamin Tissoires , Jani Nikula , Hans de Goede , Dmitry Torokhov , Adrian Salido , Jason Gerecke , linux-input , Andy Shevchenko , Mika Westerberg , Wolfram Sang , linux-i2c@vger.kernel.org, Linux Kernel , Linux Upstreaming Team Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 17, 2018 at 3:48 PM, Jarkko Nikula wrote: > Hi > > On 05/15/2018 01:20 PM, Jarkko Nikula wrote: >> >> On 05/15/2018 06:22 AM, Chris Chiu wrote: >>> >>> What if I change the 120MHz to 180MHz and then make sure that the I2C >>> operates >>> in target FS mode frequency 400kHz via scope? Would there be any side >>> effect? >>> Maybe some other busses frequency could be also affected and causing some >>> other >>> component malfunction? >>> >> Should be safe. It is only clock rate information when registering a fixed >> clock with known rate in intel-lpss.c and i2c-designware uses that info when >> calculating the timing parameters. I.e. it doesn't change any internal >> clocks. >> >> I'm trying to find a contact who can confirm what is the expected rate of >> I2C input clock and is it common to all Cannon Lake HW. >> > I got confirmation that input clock is actually even higher 216 Mhz. > > While checking does it cover all of those CNL CNL-LP and CNL-H PCI IDs may I > add your Jian-Hong, Chris and Daniel email addresses to Repored-by tags in a > fix patch? > > -- > Jarkko No problem. Thanks