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Date: Wed, 27 May 2015 04:44:41 -0700
Message-ID: <CABPqkBQ118iSB-XcRETLbkQHRu_R8y0A3TkMCu9POxpL5vUogQ@mail.gmail.com>
Subject: Re: [PATCH v2 02/11] perf/x86: Improve HT workaround GP counter constraint
From: Stephane Eranian <eranian@google.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Ingo Molnar <mingo@kernel.org>, Vince Weaver <vincent.weaver@maine.edu>,
        Jiri Olsa <jolsa@redhat.com>, "Liang, Kan" <kan.liang@intel.com>,
        LKML <linux-kernel@vger.kernel.org>
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On Wed, May 27, 2015 at 3:13 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Wed, May 27, 2015 at 02:01:04AM -0700, Stephane Eranian wrote:
>> >  #define PERF_X86_EVENT_AUTO_RELOAD     0x0400 /* use PEBS auto-reload */
>> >  #define PERF_X86_EVENT_FREERUNNING     0x0800 /* use freerunning PEBS */
>> >
>> What's free running PEBS? ;->
>
> The series here:
>
>   http://lkml.kernel.org/r/1430940834-8964-2-git-send-email-kan.liang@intel.com

Ok, I assume this goes with more patches that enable depth > 1 for the
PEBS buffer, otherwise
I am not so sure about the added value. PEBS micro-code has to
reprogram that MSR
no matter what, hasn't it?