From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751080AbdE3Qlx (ORCPT ); Tue, 30 May 2017 12:41:53 -0400 Received: from mail-it0-f48.google.com ([209.85.214.48]:35929 "EHLO mail-it0-f48.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750821AbdE3Qlv (ORCPT ); Tue, 30 May 2017 12:41:51 -0400 MIME-Version: 1.0 In-Reply-To: <20170530162838.h5tzdnrxpy6upbka@hirez.programming.kicks-ass.net> References: <37D7C6CF3E00A74B8858931C1DB2F077536F079F@SHSMSX103.ccr.corp.intel.com> <20170522192335.v4gvhz24ix2jeihg@hirez.programming.kicks-ass.net> <20170523063913.363ssgcy7kmeesye@hirez.programming.kicks-ass.net> <20170524154518.GA24144@tassilo.jf.intel.com> <20170530092523.xkuj5lqpq5pb5y4m@hirez.programming.kicks-ass.net> <20170530135128.GI24144@tassilo.jf.intel.com> <20170530162838.h5tzdnrxpy6upbka@hirez.programming.kicks-ass.net> From: Stephane Eranian Date: Tue, 30 May 2017 09:41:50 -0700 Message-ID: Subject: Re: [PATCH 1/2] perf/x86/intel: enable CPU ref_cycles for GP counter To: Peter Zijlstra Cc: Andi Kleen , Vince Weaver , "Liang, Kan" , "mingo@redhat.com" , "linux-kernel@vger.kernel.org" , "alexander.shishkin@linux.intel.com" , "acme@redhat.com" , "jolsa@redhat.com" , "torvalds@linux-foundation.org" , "tglx@linutronix.de" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, May 30, 2017 at 9:28 AM, Peter Zijlstra wrote: > On Tue, May 30, 2017 at 06:51:28AM -0700, Andi Kleen wrote: >> On Tue, May 30, 2017 at 11:25:23AM +0200, Peter Zijlstra wrote: >> > On Sun, May 28, 2017 at 01:31:09PM -0700, Stephane Eranian wrote: >> > > Ultimately, I would like to see the watchdog move out of the PMU. That >> > > is the only sensible solution. >> > > You just need a resource able to interrupt on NMI or you handle >> > > interrupt masking in software as has >> > > been proposed on LKML. >> > >> > So even if we do the soft masking, we still need to deal with regions >> > where the interrupts are disabled. Once an interrupt hits the soft mask >> > we still hardware mask. >> > >> > So to get full and reliable coverage we still need an NMI source. >> >> You would only need a single one per system however, not one per CPU. >> RCU already tracks all the CPUs, all we need is a single NMI watchdog >> that makes sure RCU itself does not get stuck. >> >> So we just have to find a single watchdog somewhere that can trigger >> NMI. > > But then you have to IPI broadcast the NMI, which is less than ideal. > > RCU doesn't have that problem because the quiescent state is a global > thing. CPU progress, which is what the NMI watchdog tests, is very much > per logical CPU though. > >> > I agree that it would be lovely to free up the one counter though. >> >> One option is to use the TCO watchdog in the chipset instead. >> Unfortunatley it's not an universal solution because some BIOS lock >> the TCO watchdog for their own use. But if you have a BIOS that >> doesn't do that it should work. > > I suppose you could also route the HPET to the NMI vector and other > similar things. Still, you're then stuck with IPI broadcasts, which > suck. > Can the HPET interrupt (whatever vector) be broadcast to all CPUs by hw? >> > One other approach is running the watchdog off of _any_ PMI, then all we >> > need to ensure is that PMIs happen semi regularly. There are two cases >> > where this becomes 'interesting': >> >> Seems fairly complex. > > Yes.. :/