From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA745C3A5A3 for ; Fri, 30 Aug 2019 05:59:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 91B1D23407 for ; Fri, 30 Aug 2019 05:59:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hRqQajhY" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727747AbfH3F7E (ORCPT ); Fri, 30 Aug 2019 01:59:04 -0400 Received: from mail-io1-f67.google.com ([209.85.166.67]:35316 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726090AbfH3F7D (ORCPT ); Fri, 30 Aug 2019 01:59:03 -0400 Received: by mail-io1-f67.google.com with SMTP id b10so11820578ioj.2; Thu, 29 Aug 2019 22:59:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7ndyanviOzu9Zi/yMi7I2hnP1XTTLaCsALOoRaimagU=; b=hRqQajhYeOFJ0Do/UKvlZ8YCLqMFgsPu9EaM4WuZXWKonIayGwNzasBLgYD79HRu3l mqIdo+C/hZhohTNBxV8l+jqpWs4plJQa/3N3Tw24kuLkXrUqfLa8gxpTfcOL3iCx5r4h 9WEUrhFm7NZ3ZU8Ey3ak/eigW3IShywzQ620MydDC+zYncJAaCSa+bjufjqDaZcIzWZ/ U9BPEnUxTe/4C2dPPAxrbC6mHwAP8o1po8Hqy1WGrpUKFzQoVYVvHxWPQDWN9TqYyAkP eQb+lUgQbKcWXeCV4VgAfZ+5Hl199GefB+fulgZg0XuHxzCfOZuI/MnKql4kigbPwJZU uRBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7ndyanviOzu9Zi/yMi7I2hnP1XTTLaCsALOoRaimagU=; b=KG7W5Ul8SSTeWxfOcVmOkkcxSYMGERxoeo2qu4dbiYuyggSgl1OcoCdwcmaWHaAPiL vQIxyOaZ+YXX0KwSQXXgULDqCzUvcPGqVNR+j+5QIVveTgUJkvQJlLW2peGc6nbgQpP7 SIdKh+Rk2CXqJQxhZC6tKR7g2tEvSkUhq/IW0Yb4U+Jj/jSEDe5DABgmVXIjoB/nfZlT bCVTJoL465TGuj/c65Ovb37OetuunzBz5xafhHLRU8UERw1oTEag306ssU94CwJdHGwm WOLv0D3o6U3ev3WOuV85lU0PATJ8FvqztBkov7z1z3qbNL9Q6P6JPIDIw3zNV9VyZ/iw iMWw== X-Gm-Message-State: APjAAAVNTF3ir7xVfS4o2oy1gnG600OFQNKJQkPYXmJm66dNl4NlV0W3 cbjR/EY/fraEUStQUp8uAMsRyP8svjEFBXa10nQ= X-Google-Smtp-Source: APXvYqz7HprZ4bcyYVV3mIF6aHucW/Znj2uC3GMS+aDtrA6tv/yEaG9x13MjchExSuH4RftaJHub77QchQjdK82qeBw= X-Received: by 2002:a6b:6516:: with SMTP id z22mr9438882iob.7.1567144742526; Thu, 29 Aug 2019 22:59:02 -0700 (PDT) MIME-Version: 1.0 References: <1567004515-3567-1-git-send-email-peng.fan@nxp.com> <1567004515-3567-2-git-send-email-peng.fan@nxp.com> In-Reply-To: <1567004515-3567-2-git-send-email-peng.fan@nxp.com> From: Jassi Brar Date: Fri, 30 Aug 2019 00:58:51 -0500 Message-ID: Subject: Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox To: Peng Fan Cc: "robh+dt@kernel.org" , "mark.rutland@arm.com" , "sudeep.holla@arm.com" , "andre.przywara@arm.com" , "f.fainelli@gmail.com" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , dl-linux-imx Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 27, 2019 at 10:02 PM Peng Fan wrote: > > From: Peng Fan > > The ARM SMC/HVC mailbox binding describes a firmware interface to trigger > actions in software layers running in the EL2 or EL3 exception levels. > The term "ARM" here relates to the SMC instruction as part of the ARM > instruction set, not as a standard endorsed by ARM Ltd. > > Signed-off-by: Peng Fan > --- > .../devicetree/bindings/mailbox/arm-smc.yaml | 125 +++++++++++++++++++++ > 1 file changed, 125 insertions(+) > create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.yaml > > diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.yaml b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml > new file mode 100644 > index 000000000000..f8eb28d5e307 > --- /dev/null > +++ b/Documentation/devicetree/bindings/mailbox/arm-smc.yaml > @@ -0,0 +1,125 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mailbox/arm-smc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: ARM SMC Mailbox Interface > + > +maintainers: > + - Peng Fan > + > +description: | > + This mailbox uses the ARM smc (secure monitor call) and hvc (hypervisor > + call) instruction to trigger a mailbox-connected activity in firmware, > + executing on the very same core as the caller. By nature this operation > + is synchronous and this mailbox provides no way for asynchronous messages > + to be delivered the other way round, from firmware to the OS, but > + asynchronous notification could also be supported. However the value of > + r0/w0/x0 the firmware returns after the smc call is delivered as a received > + message to the mailbox framework, so a synchronous communication can be > + established, for a asynchronous notification, no value will be returned. > + The exact meaning of both the action the mailbox triggers as well as the > + return value is defined by their users and is not subject to this binding. > + > + One use case of this mailbox is the SCMI interface, which uses shared memory > + to transfer commands and parameters, and a mailbox to trigger a function > + call. This allows SoCs without a separate management processor (or when > + such a processor is not available or used) to use this standardized > + interface anyway. > + > + This binding describes no hardware, but establishes a firmware interface. > + Upon receiving an SMC using one of the described SMC function identifiers, > + the firmware is expected to trigger some mailbox connected functionality. > + The communication follows the ARM SMC calling convention. > + Firmware expects an SMC function identifier in r0 or w0. The supported > + identifiers are passed from consumers, or listed in the the arm,func-ids > + properties as described below. The firmware can return one value in > + the first SMC result register, it is expected to be an error value, > + which shall be propagated to the mailbox client. > + > + Any core which supports the SMC or HVC instruction can be used, as long as > + a firmware component running in EL3 or EL2 is handling these calls. > + > +properties: > + compatible: > + const: arm,smc-mbox > + > + "#mbox-cells": > + const: 1 > + > + arm,num-chans: > + description: The number of channels supported. > + items: > + minimum: 1 > + maximum: 4096 # Should be enough? > + > + method: > + - enum: > + - smc > + - hvc > + > + transports: > + - enum: > + - mem > + - reg > + > + arm,func-ids: > + description: | > + An array of 32-bit values specifying the function IDs used by each > + mailbox channel. Those function IDs follow the ARM SMC calling > + convention standard [1]. > + > + There is one identifier per channel and the number of supported > + channels is determined by the length of this array. > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 0 > + maxItems: 4096 # Should be enough? > + > +required: > + - compatible > + - "#mbox-cells" > + - arm,num-chans > + - transports > + - method > + > +examples: > + - | > + sram@910000 { > + compatible = "mmio-sram"; > + reg = <0x0 0x93f000 0x0 0x1000>; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges = <0 0x0 0x93f000 0x1000>; > + > + cpu_scp_lpri: scp-shmem@0 { > + compatible = "arm,scmi-shmem"; > + reg = <0x0 0x200>; > + }; > + > + cpu_scp_hpri: scp-shmem@200 { > + compatible = "arm,scmi-shmem"; > + reg = <0x200 0x200>; > + }; > + }; > + > + firmware { > + smc_mbox: mailbox { > + #mbox-cells = <1>; > + compatible = "arm,smc-mbox"; > + method = "smc"; > + arm,num-chans = <0x2>; > + transports = "mem"; > + /* Optional */ > + arm,func-ids = <0xc20000fe>, <0xc20000ff>; > SMC/HVC is synchronously(block) running in "secure mode", i.e, there can only be one instance running platform wide. Right? That implies there is only one physical channel in the platform. So if you need to initiate different functions (tx, rx), you call them sequentially by changing the func-id for each request. Why not? -Jassi