From: Kamal Dasu <kdasu.kdev@gmail.com>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: bcm-kernel-feedback-list <bcm-kernel-feedback-list@broadcom.com>,
Mark Brown <broonie@kernel.org>,
linux-spi <linux-spi@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
Date: Mon, 20 Apr 2020 11:12:21 -0400 [thread overview]
Message-ID: <CAC=U0a1mOWo3ucMJ7x5wuWQ44NRA2+Dj6fKAi1dbevNaxcYJzA@mail.gmail.com> (raw)
In-Reply-To: <63176468-53b6-c11a-9e33-2ca9dd06f7a3@gmail.com>
Yes missed this one.
Should I send a v3 of the entire set.
Kamal
On Sun, Apr 19, 2020 at 3:44 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> Hi Kamal,
>
> On 4/19/2020 12:23 PM, Kamal Dasu wrote:
> > Older MIPS chips have a QSPI/MSPI controller that does not have the
> > MSPI_REV offset, reading from that offset will cause a bus error. Match
> > their compatible string and do not perform a read from that register in
> > that case.
> >
> > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> > Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
>
> This patch should also have a From: that is from me.
> --
> Florian
next prev parent reply other threads:[~2020-04-20 15:12 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20200419192339.32023-1-kdasu.kdev@gmail.com>
2020-04-19 19:23 ` [Patch v2 1/9] spi: bcm-qspi: Handle clock probe deferral Kamal Dasu
2020-04-19 19:23 ` [Patch v2 2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs Kamal Dasu
2020-04-19 19:23 ` [Patch v2 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset Kamal Dasu
2020-04-19 19:44 ` Florian Fainelli
2020-04-20 15:12 ` Kamal Dasu [this message]
2020-04-20 15:17 ` Mark Brown
2020-04-19 19:23 ` [Patch v2 4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change Kamal Dasu
2020-04-19 19:23 ` [Patch v2 5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0 Kamal Dasu
2020-04-19 19:23 ` [Patch v2 6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management Kamal Dasu
2020-04-19 19:23 ` [Patch v2 7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds Kamal Dasu
2020-04-19 19:23 ` [Patch v2 8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz Kamal Dasu
2020-04-19 19:23 ` [Patch v2 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers Kamal Dasu
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