From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.6 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DEE8AC433E1 for ; Sun, 2 Aug 2020 00:30:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B137620829 for ; Sun, 2 Aug 2020 00:30:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="wKoGwjku" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727889AbgHBAaz (ORCPT ); Sat, 1 Aug 2020 20:30:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725883AbgHBAaz (ORCPT ); Sat, 1 Aug 2020 20:30:55 -0400 Received: from mail-lf1-x142.google.com (mail-lf1-x142.google.com [IPv6:2a00:1450:4864:20::142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8ECD0C06174A for ; Sat, 1 Aug 2020 17:30:54 -0700 (PDT) Received: by mail-lf1-x142.google.com with SMTP id i19so18699084lfj.8 for ; Sat, 01 Aug 2020 17:30:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=ec1r1tZZhLtfRlggg/zu2nnszPLvqXC5YM2YU2HZuDY=; b=wKoGwjkuSquBXSKd6RQTvt7/zMJOD7H7+imD5zHmg2L+H3t4gEloPd3kF9yxhTiKah lcGEhT4ciyCYaQXp6iTsxq1Y+wXANY1zKai63JAImoVEPGHaKdD/nOWoCUblOXZrRR8Y RB479LKYTs136EmsDMlL4+Ck42tQrqHTmc9F63RooE6wGfKPBVgSdYvjBlBynHtowKXl u60iHZeaLoli3mfMFJCkjHRH9QFu/ioE5Rmjywxz2jrHFJep3npflS7SGfHTYjZq32dw rOikI4QTI/T38HN7+KdelWoEX+t9oBhkkv955OoeO3pxBWpN0whSIxl978qh5lUUqY9g p3bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=ec1r1tZZhLtfRlggg/zu2nnszPLvqXC5YM2YU2HZuDY=; b=gjzhH1oZHD4pdu9kVE4mSnU9ljXOnozJcXRzmE/V43QNFA+rmnZIP7GZZorQQQtJVl CjMpaFh69u7lu09H8TBTXwIrPRSviVQ85q8Oxm2QhseTSj//8UCww8h+tDMV+g1fwA0U JADsa9A0zSN0pN7B28eAPaYJKIAXJcyRN+U01UcUrNXDMNQT7jmnwy4kCnRkWMhCC5XG vTir4ctwGOhH45j5DPFQ4ymtq05olKu6eAKITVWXWTN0zOI2mpx5xNRM5F9onowE/UAo A54+jKUT3T7QyTTXkl5SN3ZdwMUaGdtmNy4/JAjxxFvS8iplVk47Vd1fnMYqEfQTBN+K IV+g== X-Gm-Message-State: AOAM531gg/o3/oMwtkQmxJUa6c5T7GXyU/sIro8GCk9saNiOApWmmZxo rKytLm+7fOH7g2ElJBV5dGn/I1ssRfNo8KaSgtR3Xw== X-Google-Smtp-Source: ABdhPJzPXTK3nzbTrtPHobAj0f/c0JCHdGHR3VQ22y/pyzxyJ8CpjPrgjT8x7nBt5Sb8DqcWMe+ntDTKifLmxyIc7Rk= X-Received: by 2002:a19:8705:: with SMTP id j5mr5098223lfd.122.1596328252690; Sat, 01 Aug 2020 17:30:52 -0700 (PDT) MIME-Version: 1.0 References: <20200714201540.3139140-1-rajatja@google.com> In-Reply-To: From: Rajat Jain Date: Sat, 1 Aug 2020 17:30:15 -0700 Message-ID: Subject: Re: [PATCH v5] PCI/ACS: Enable PCI_ACS_TB and disable only when needed for ATS To: Rajat Jain Cc: David Woodhouse , Lu Baolu , Joerg Roedel , Bjorn Helgaas , "Rafael J. Wysocki" , Len Brown , "open list:AMD IOMMU (AMD-VI)" , Linux Kernel Mailing List , linux-pci , ACPI Devel Maling List , Raj Ashok , "Krishnakumar, Lalithambika" , Mika Westerberg , Jean-Philippe Brucker , Prashant Malani , Benson Leung , Todd Broch , Alex Levin , Mattias Nissler , Bernie Keany , Aaron Durbin , Diego Rivas , Duncan Laurie , Furquan Shaikh , Jesse Barnes , Christian Kellner , Alex Williamson , Greg Kroah-Hartman , "Oliver O'Halloran" , Saravana Kannan , Suzuki K Poulose , Arnd Bergmann , Heikki Krogerus Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bjorn, On Tue, Jul 14, 2020 at 1:24 PM Rajat Jain wrote: > > On Tue, Jul 14, 2020 at 1:15 PM Rajat Jain wrote: > > > > The ACS "Translation Blocking" bit blocks the translated addresses from > > the devices. We don't expect such traffic from devices unless ATS is > > enabled on them. A device sending such traffic without ATS enabled, > > indicates malicious intent, and thus should be blocked. > > > > Enable PCI_ACS_TB by default for all devices, and it stays enabled until > > atleast one of the devices downstream wants to enable ATS. It gets > > disabled to enable ATS on a device downstream it, and then gets enabled > > back on once all the downstream devices don't need ATS. > > > > Signed-off-by: Rajat Jain Just checking to see if you got a chance to look at this V5 patch. Thanks & Best Regards, Rajat > > --- > > Note that I'm ignoring the devices that require quirks to enable or > > disable ACS, instead of using the standard way for ACS configuration. > > The reason is that it would require adding yet another quirk table or > > quirk function pointer, that I don't know how to implement for those > > devices, and will neither have the devices to test that code. > > > > v5: Enable TB and disable ATS for all devices on boot. Disable TB later > > only if needed to enable ATS on downstream devices. > > v4: Add braces to avoid warning from kernel robot > > print warning for only external-facing devices. > > v3: print warning if ACS_TB not supported on external-facing/untrusted ports. > > Minor code comments fixes. > > v2: Commit log change > > > > drivers/pci/ats.c | 5 ++++ > > drivers/pci/pci.c | 57 +++++++++++++++++++++++++++++++++++++++++++++ > > drivers/pci/pci.h | 2 ++ > > drivers/pci/probe.c | 2 +- > > include/linux/pci.h | 2 ++ > > 5 files changed, 67 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/ats.c b/drivers/pci/ats.c > > index b761c1f72f67..e2ea9083f30f 100644 > > --- a/drivers/pci/ats.c > > +++ b/drivers/pci/ats.c > > @@ -28,6 +28,9 @@ void pci_ats_init(struct pci_dev *dev) > > return; > > > > dev->ats_cap = pos; > > + > > + dev->ats_enabled = 1; /* To avoid WARN_ON from pci_disable_ats() */ > > + pci_disable_ats(dev); > > } > > > > /** > > @@ -82,6 +85,7 @@ int pci_enable_ats(struct pci_dev *dev, int ps) > > } > > pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); > > > > + pci_disable_acs_trans_blocking(dev); > > dev->ats_enabled = 1; > > return 0; > > } > > @@ -102,6 +106,7 @@ void pci_disable_ats(struct pci_dev *dev) > > ctrl &= ~PCI_ATS_CTRL_ENABLE; > > pci_write_config_word(dev, dev->ats_cap + PCI_ATS_CTRL, ctrl); > > > > + pci_enable_acs_trans_blocking(dev); > > dev->ats_enabled = 0; > > } > > EXPORT_SYMBOL_GPL(pci_disable_ats); > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > > index 73a862782214..614e3c1e8c56 100644 > > --- a/drivers/pci/pci.c > > +++ b/drivers/pci/pci.c > > @@ -876,6 +876,9 @@ static void pci_std_enable_acs(struct pci_dev *dev) > > /* Upstream Forwarding */ > > ctrl |= (cap & PCI_ACS_UF); > > > > + /* Translation Blocking */ > > + ctrl |= (cap & PCI_ACS_TB); > > + > > pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); > > } > > > > @@ -904,6 +907,60 @@ static void pci_enable_acs(struct pci_dev *dev) > > pci_disable_acs_redir(dev); > > } > > > > +void pci_disable_acs_trans_blocking(struct pci_dev *pdev) > > +{ > > + u16 cap, ctrl, pos; > > + struct pci_dev *dev; > > + > > + if (!pci_acs_enable) > > + return; > > + > > + for (dev = pdev; dev; dev = pci_upstream_bridge(pdev)) { > > + > > + pos = dev->acs_cap; > > + if (!pos) > > + continue; > > + > > + /* > > + * Disable translation blocking when first downstream > > + * device that needs it (for ATS) wants to enable ATS > > + */ > > + if (++dev->ats_dependencies == 1) { > > I am a little worried about a potential race condition here. I know > that 2 PCI devices cannot be enumerating at the same time. Do we know > if multiple pci_enable_ats() and pci_disable_ats() function calls can > be simultaneously executing (even for different devices)? If so, we > may need an atomic_t variable for ats_dependencies. > > Thanks, > > Rajat > > > > + pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); > > + pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); > > + ctrl &= ~(cap & PCI_ACS_TB); > > + pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); > > + } > > + } > > +} > > + > > +void pci_enable_acs_trans_blocking(struct pci_dev *pdev) > > +{ > > + u16 cap, ctrl, pos; > > + struct pci_dev *dev; > > + > > + if (!pci_acs_enable) > > + return; > > + > > + for (dev = pdev; dev; dev = pci_upstream_bridge(pdev)) { > > + > > + pos = dev->acs_cap; > > + if (!pos) > > + continue; > > + > > + /* > > + * Enable translation blocking when last downstream device > > + * that depends on it (for ATS), doesn't need ATS anymore > > + */ > > + if (--dev->ats_dependencies == 0) { > > + pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap); > > + pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl); > > + ctrl |= (cap & PCI_ACS_TB); > > + pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl); > > + } > > + } > > +} > > + > > /** > > * pci_restore_bars - restore a device's BAR values (e.g. after wake-up) > > * @dev: PCI device to have its BARs restored > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > > index 12fb79fbe29d..f5d8ecb6ba96 100644 > > --- a/drivers/pci/pci.h > > +++ b/drivers/pci/pci.h > > @@ -552,6 +552,8 @@ static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) > > return -ENOTTY; > > } > > #endif > > +void pci_disable_acs_trans_blocking(struct pci_dev *dev); > > +void pci_enable_acs_trans_blocking(struct pci_dev *dev); > > > > /* PCI error reporting and recovery */ > > pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > > index 8c40c00413e7..e2ff3a94e621 100644 > > --- a/drivers/pci/probe.c > > +++ b/drivers/pci/probe.c > > @@ -2387,10 +2387,10 @@ static void pci_init_capabilities(struct pci_dev *dev) > > pci_vpd_init(dev); /* Vital Product Data */ > > pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ > > pci_iov_init(dev); /* Single Root I/O Virtualization */ > > + pci_acs_init(dev); /* Access Control Services */ > > pci_ats_init(dev); /* Address Translation Services */ > > pci_pri_init(dev); /* Page Request Interface */ > > pci_pasid_init(dev); /* Process Address Space ID */ > > - pci_acs_init(dev); /* Access Control Services */ > > pci_ptm_init(dev); /* Precision Time Measurement */ > > pci_aer_init(dev); /* Advanced Error Reporting */ > > pci_dpc_init(dev); /* Downstream Port Containment */ > > diff --git a/include/linux/pci.h b/include/linux/pci.h > > index 7a40cd5caed0..31da4355f0fd 100644 > > --- a/include/linux/pci.h > > +++ b/include/linux/pci.h > > @@ -480,6 +480,8 @@ struct pci_dev { > > u16 ats_cap; /* ATS Capability offset */ > > u8 ats_stu; /* ATS Smallest Translation Unit */ > > #endif > > + /* Total number of downstream devices below a bridge that need ATS */ > > + u8 ats_dependencies; > > #ifdef CONFIG_PCI_PRI > > u16 pri_cap; /* PRI Capability offset */ > > u32 pri_reqs_alloc; /* Number of PRI requests allocated */ > > -- > > 2.27.0.389.gc38d7665816-goog > >