From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07E2EC433EF for ; Tue, 7 Sep 2021 20:53:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E39F061051 for ; Tue, 7 Sep 2021 20:53:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346038AbhIGUya (ORCPT ); Tue, 7 Sep 2021 16:54:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229601AbhIGUy2 (ORCPT ); Tue, 7 Sep 2021 16:54:28 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79B03C061575 for ; Tue, 7 Sep 2021 13:53:21 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id y34so335752lfa.8 for ; Tue, 07 Sep 2021 13:53:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=C2nsQAg7kmIjIclpBrhtqlSTKrFIqUX3LxjUhDb/REE=; b=YCsQ08Usmp+NSFE2q8Vqqu+1k2Jxc19NJXOmL6Zp4reeKHQuFtk9hbHHDQ1Xmgd0m6 bshPY/6nYk77pyO6ANj4wcbRwCSQa3QJ+vwudNf14BMBAQkxF89NI98nGh+WXthFEtpF 5LV1zH69hfTjOdeQXh4bCWiJk6dplQNZp4kzI8t6aC8egWr7xwOHRDBBQEJqzp0P1BDl oHW89Ks9NHvUdtb9B3/rPkLOrYYDG3mpEf6+0nLOinqyHGlamXgbr/mEN/xCcKNiLapd 6X+s0483+WA7SUQ5DE6qWrfJjZG3v8EsCt7AyCAnzxOW4A32rKdP6sCZxRm7mCBrh9oj G/ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=C2nsQAg7kmIjIclpBrhtqlSTKrFIqUX3LxjUhDb/REE=; b=NHSzq7k5FEfMluZBOfS9Yw9naiexhZ9g8XLhQfDzWaRHTTtbrzFrUCwpl6lZrmJWuo wG5HTLsFD0bCLFmurXrhqtwhDdtHrKdG4NrdWvZTfcBmGS6UZr3VU2wMfT5ZBvxcC87M UtlFk67MYZm78esVf71KurEVSLF/ua79jPrsQyjhfRucIj4APWfVq1t7y7sHA5grE6+y 1DWn8OBOe1hnzuFXnYY4ALfyGO4WULL6BsXGZBw6s9hLpD0prYHESMCgNJRH9EpqN2lc HXouurkfl/EL7JA3pAuiX9IDHTRmHS54+QDNocfCuRK9kR59oM/s9GLXx7VJr6fpgXz0 +0+g== X-Gm-Message-State: AOAM532FI4x1axe6oh9yQtGpsN9nfN0txP0vBqlmugNiudo2rWBd//Qh TMMxbv1UkXaU7MM0vSnw5BQJ/hoAvvWHaQWbl68lZQ== X-Google-Smtp-Source: ABdhPJzhBFK+nc5T6nsZ3d/UNCMCN4OBLlDwQPAjHtpwLPGtbms1OHE1axqApJ9PGJSVbkInMFi0jFJ5cFAgNd5Hu4M= X-Received: by 2002:a05:6512:e89:: with SMTP id bi9mr207568lfb.95.1631047999878; Tue, 07 Sep 2021 13:53:19 -0700 (PDT) MIME-Version: 1.0 References: <1630065205-7618-1-git-send-email-wenbin.mei@mediatek.com> <1630065205-7618-2-git-send-email-wenbin.mei@mediatek.com> In-Reply-To: <1630065205-7618-2-git-send-email-wenbin.mei@mediatek.com> From: Linus Walleij Date: Tue, 7 Sep 2021 22:53:08 +0200 Message-ID: Subject: Re: [PATCH v1 1/2] dt-bindings: mmc: mtk-sd: add hs400 dly3 setting To: Wenbin Mei Cc: Ulf Hansson , Rob Herring , Matthias Brugger , Chaotian Jing , Avri Altman , Wolfram Sang , Yoshihiro Shimoda , Yue Hu , Adrian Hunter , Bean Huo , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux ARM , "moderated list:ARM/Mediatek SoC support" , linux-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Aug 27, 2021 at 1:53 PM Wenbin Mei wrote: > Add hs400 dly3 setting for mtk-sd yaml > > Signed-off-by: Wenbin Mei (...) > + mediatek,hs400-ds-dly3: > + $ref: /schemas/types.yaml#/definitions/uint32 > + description: > + HS400 DS dly3 delay setting. > + minimum: 0 > + maximum: 31 Which unit is this? Clock cycles? Then please write that in the binding description. Yours, Linus Walleij